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Synthesis and Mapping for Application-Specific Processor Networks

Synthesis and Mapping for Application-Specific Processor Networks
特定应用处理器网络的综合和映射
批准号:
0903541
负责人:
Jason Cong
金额:
$33.9万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2009
资助国家:
美国
项目状态:
已结题
起止时间:
2009-07-15 至 2015-12-31

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中文摘要
翻译
提案ID:0903541 PI姓名:Cong,Jason Inst.:加州大学洛杉矶分校题目:专用处理器网络的综合和映射摘要:电子工业在设计复杂性和生产率方面面临着巨大的挑战。今天吗?的复杂系统芯片(SOC)设计具有超过十亿个晶体管,并且需要许多人年来设计,导致过高的设计成本。 该项目的目标是显著提高电子系统的设计生产力,以实现具有成本效益的创新。在这个建议中,PI探索的概念,使用一个集合的应用程序特定的处理器作为一个通用平台的设计和实现的特定领域的SOC,可用于多个应用程序在一个共同的领域,以摊销的设计时间和成本。这样的平台可以由多个固定的和可定制的处理器、定制的逻辑块、现场可编程逻辑块和可定制的片上网络组成。实际上,PI正在将用于专用集成电路设计的基于标准单元的方法扩展到用于嵌入式系统设计的基于专用处理器的设计方法。所提出的设计方法将大大提高设计抽象的水平,从而提高电子设计的生产力和成本,并实现具有成本效益的创新。这个项目还包括研究和教育的融合?该项目将通过新的课程和个人学习向研究生和高年级本科生展示该项目的新概念和研究成果。综合研究和教育计划还旨在通过与其他专注于多样性的校园组织合作,吸引代表性不足的学生,如加州大学洛杉矶分校卓越工程与多样性中心和女工程师协会。
英文摘要
Proposal ID: 0903541 PI name: Cong, Jason Inst.:U of Cal Los Angeles Title: Synthesis and Mapping for Application-Specific Processor NetworksAbstract:The electronic industry is facing great challenge in terms of design complexity and productivity. Today?s complex system-on-a-chip (SOC) design has over one billion transistors and requires many man-years to design, resulting prohibitively high design cost. The goal of this project is to significantly improve the design productivity for electronic systems to enable cost-efficient innovation. In this proposal the PIs explore the concept of using a collection of application-specific processors as a general platform for design and implementation of a domain-specific SOC which can be used for multiple applications in a common domain to amortize the design time and cost. Such a platform may consist of a number of fixed and customizable processors, customized logic blocks, field-programmable logic blocks, and a customizable network-on-chip. Effectively, the PIs are extending the standard cell-based methodology for application-specific integrated circuit designs to the application-specific processor-based design methodology for embedded system designs. The proposed design methodology will significantly raise the level of design abstraction, in turn improve the electronic design productivity and cost, and enable cost-efficient innovation. This project also includes the integration of research and education ? the project will expose the new concepts and research results from this project to graduate students and upper-division undergraduate students via new courses and individual studies. The integrated research and education program is also designed to attract underrepresented students via partnership with other campus organizations focused on diversity, such as the UCLA Center for Excellence in Engineering and Diversity and the Society of Woman Engineers.
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会议论文
Collaborative Research: FET: Medium: Efficient Compilation for Dynamically Reconfigurable Atom Arrays
SHF: Medium: Automating High Level Synthesis via Graph-Centric Deep Learning
RTML: Large: Acceleration to Graph-Based Machine Learning
CAPA: Collaborative Research: A Multi-Paradigm Programming Infrastructure for Heterogeneous Architectures
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