SHF: Small: Hardware-Software Co-Design for Next Generation Packet Forwarding Engines

互联网主干，包括核心路由器和边缘路由器，正变得更加灵活、可扩展和可编程，以支持下一代互联网的未来创新。虽然互联网路由器的功能在不断发展，但其性能仍然是实际部署中的一个主要问题。传统上，核心路由器的设计使用吞吐量作为关键性能指标。在吞吐量要求持续增长的同时，峰值功率和总能耗已成为核心路由器以及其他网络设备设计中的额外重要考虑因素。虽然三值内容可寻址存储器(TCAM)已被广泛用于分组转发，但它们的功耗性能较差。本文研究了使用静态随机存取存储器(SRAM)和现场可编程门阵列(FP GA)/专用集成电路(ASIC)相结合的低功耗存储技术，为包括IP查找、路由器虚拟化、分组分类和灵活的流处理(如OpenFlow)在内的各种分组转发引擎开发高吞吐量和高能效的解决方案。下一代路由器和交换机中的分组转发引擎使用硬件-软件协同设计框架进行设计。基于该框架，除了吞吐量之外，还使用功率(包括能量)作为关键性能指标来开发新的体系结构和算法。具体地说，为了弥合软件和硬件开发之间的差距，开发并验证了用于分组转发引擎的硬件实现的高级功率-性能模型。这些模型有助于设计各种启发式算法和架构，用于虚拟化IP查找、多字段数据包分类和灵活的流处理。这项工作不是非常流行的基于TCAM的解决方案，而是专注于基于SRAM的并行和流水线体系结构。研究了包括分区、时钟门控、功率感知数据结构设计和功率感知负载平衡在内的新技术，以同时提高吞吐量和降低功率和/或能量消耗

The Internet backbone, including both core and edge routers, is becoming more flexible, scalable and programmable to enable future innovations in the next generation Internet. While the functionality of Internet routers evolves, the performance remains a major concern for real-life deployment. Traditionally, core routers have been designed using throughput as a key performance metric. While the throughput requirements continue to grow, peak power and total energy dissipated have emerged as additional critical considerations in the design of core routers as well as in other network equipment. Although ternary content addressable memories (TCAMs) have been widely used for packet forwarding, they have poor power performance. This work studies the use of low-power memory technology such as the static random access memory (SRAM) combined with field-programmable gate arrays (FPGAs) / application-specific integrated circuits (ASICs) to develop high-throughput and power-efficient solutions for various packet forwardingengines including IP lookup, router virtualization, packet classification and flexible flow processing (e.g., OpenFlow). Packet forwarding engines in next generation routers and switches are designed using a hardware-software co-design framework. Based on this framework, novel architectures and algorithms are developed using power (including energy) as a key performance metric in addition to throughput. Specifically, to bridge the gap between software and hardware development, high-level power-performance models for hardware implementations of packet forwarding engines are developed and validated. These models facilitate design of various heuristics for power-efficient algorithms and architectures for virtualized IP lookup, multi-field packet classification and flexible flow processing. Instead of the highly popular TCAM based solutions, this work focuses on SRAM-based parallel and pipeline architectures. Novel techniques including partitioning, clock gating, power-aware data structure design and power-aware load balancing are studied to simultaneously increase throughput and reduce power and/or energy dissipation