SHF: Small: High Quality Test and Post-Silicon Validation of System-On-Chip Integrated Circuits

测试微处理器和其他芯片以验证它们的时钟频率称为延迟测试。如果测试错误，而3 GHz芯片实际上是2.99 GHz芯片，客户系统可能会随机崩溃。但如果测试错误，2.8 GHz的芯片真的会以3 GHz的速度运行，制造商就会赔钱，因为他们把3 GHz的芯片作为低价的2.8 GHz芯片出售。如今，准确地确定高速芯片的时钟频率是昂贵的。该项目正在开发新的测试技术，以降低精确制造测试的成本，从而降低芯片价格。当手机和平板电脑等产品中的芯片堆叠在一起时，准确的延迟测试变得更加困难，因为一个芯片的噪音会影响相邻芯片的速度。这个项目的更广泛影响是教育学生在半导体和电子行业进行高级开发和研究，无论是通过直接参与该项目，还是通过使用项目成果的课程。这项研究的成果将分发给学术界和产业界。更长期、更广泛的影响是，高级消费产品中堆叠芯片的成本降低速度加快，以负担得起的价格提供更多功能，并具有理想的重量、尺寸和电池寿命。

Testing microprocessors and other chips to verify their clock rate is known as delay testing. If the test is wrong, and a 3 GHz chip is really a 2.99 GHz chip, the customer system may randomly crash. But if the test is wrong and a 2.8 GHz chip will really run at 3 GHz, the manufacturer loses money by selling the 3 GHz chip as a lower-priced 2.8 GHz chip. Today it is expensive to accurately determine the clock rate of high-speed chips. This project is developing new test techniques to lower the cost of accurate manufacturing tests, so that chip prices can be reduced. Accurate delay testing becomes even more challenging when chips are stacked together in products such as cell phones and tablets, since noise from one chip can influence the speed of its neighbors.The broader impact of this project is in educating students to do advanced development and research in the semiconductor and electronics industries, both by directly working on the project, and through courses that use the project results. The results of this research will be distributed to academia and industry. A longer-term broader impact is acceleration of cost reductions in stacked chips in advanced consumer products, providing more functionality at an affordable price with desirable weight, size, and battery life.