SHF: Small: A Brick in the Wall: Achieving Yield, Performance and Density Effective DRAM Beyond 22nm Technology

四十多年来，计算机主存储器主要使用动态随机存取存储器（DRAM）。该技术是一种成熟的商品，已在成本，性能，容量和能源之间进行了优化和平衡。很多DRAM？DRAM的成功是由于内存中硅器件的不断缩小，这使得DRAM的容量大约每两年翻一番，满足了当今对更多内存容量的迫切需求。S和明天？的应用。 然而，一个关键问题在于器件尺寸的缩小：它正在停止，主要是由于制造工艺无法精确控制器件的尺寸，这被称为工艺变化（PV）。PV有一些已知的问题。然而，在过去很少被调查的一个重要问题是，PV可以导致关键的存储器操作时序违规。这种违规行为削减了DRAM芯片的产量，并立即增加了芯片成本。解决这一挑战对于DRAM行业的未来至关重要，DRAM行业对成本和利润高度敏感。本研究旨在解决PV对DRAM器件时序和芯片成品率带来的挑战。 我们的关键方法是暴露由PV引起的继承操作时序变化，以便它们可以由存储器控制器在外部进行管理。这种方法通过允许更多的DRAM芯片满足设计规范，在不损害芯片密度的情况下，以暴露的时序可变性换取增强的芯片产量。由于时序变化导致应用程序的性能损失，我们提出了一套技术，逐步减轻损失所产生的变化与更深的技术扩展。我们的假设是，由于技术缩放和PV的威胁，产量损失可以很好地控制与我们的渐进机制，如果现有的存储器操作的时序约束可以适应PV引起的速度变化。这项研究的更广泛影响是使DRAM技术能够持续扩展，以实现未来工程，科学，生物，环境，商业和消费应用计算的成本，容量和性能要求。本科生和研究生都将通过该项目提供的研究和教育机会进行招募和培训。

For more than four decades, computer main memory has predominantly used Dynamic Random Access Memory (DRAM). This technology is a mature commodity that has been optimized and balanced among cost, performance, capacity and energy. Much of DRAM?s success is due to continuous shrinking of the silicon devices in the memory, which allows DRAM capacity to double roughly every two years, satisfying the aggressive need for more memory capacity of today?s and tomorrow?s applications. Yet, a critical problem lies in the shrinking of the device dimensions: It is coming to a halt largely due to the inability of the manufacturing process to precisely control the sizes of a device, which is termed process variation (PV). There are some known problems with PV. However, a vital problem that has rarely been investigated in the past is that PV can cause critical memory operational timing violations. Such violations slash DRAM chip yield, and immediately increase the chip cost. Solving this challenge is crucial to the future of the DRAM industry, which is highly sensitive to cost and profit.This research aims to address the challenge imposed by PV on DRAM device timing to chip yield. Our key approach is to expose inherit operational timing variations caused by PV, so that they can be managed externally by the memory controller. This approach trades exposed timing variability for enhanced chip yield, without harming chip density, by allowing more DRAM chips to meet design specifications. Since the timing variations lead to application performance loss, we propose a suite of techniques that progressively mitigate the loss arising from increasing variance with deeper technology scaling. Our hypothesis is that the threat to yield loss due to technology scaling and PV can be well controlled with our progressive mechanisms, if existing timing constraints for memory operations can adapt to PV-induced speed variations. The broader impact of this research is to enable the continuous scaling of the DRAM technology to achieve the cost, capacity and performance requirement for future computing in engineering, scientific, biological, environmental, business and consumer applications. Both undergraduate and graduate students will be recruited and trained through research and education opportunities provided by this project.