SHF: Small: Test Chip Design for Maximal Yield Learning

集成电路无处不在，从移动的电话和电视到汽车和飞机，几乎无处不在。为了继续生产新的和更有能力的电子器件，有必要开发用于创建示例电子系统的技术，该示例电子系统提供关于如何改进集成电路的设计和制造的关键信息。这个由NSF资助的项目专注于开发一种设计方法，用于创建与手机，电视等实际使用的电子产品非常相似的集成电路，但也具有当它们由于设计和/或制造中的非理想性而无法正常工作时可以轻松诊断的特性。从诊断中学到的知识然后将允许设计和制造被改进，以便减少/防止用于实际产品（电话、汽车等）的集成电路。在NSF计划的支持下，将开发基于逻辑功能规则性的集成电路设计方法学。计划的方法产生的测试电路，反映了日常产品中使用的实际集成电路的各种物理方面，同时保证最佳的测试和诊断特性。 该方法将使集成电路的设计者和制造商能够为未来的产品生产新的、功能更强大的集成电子产品。示例电路将与工业合作伙伴合作设计和制造，以展示该方法的能力。

Integrated circuits are pervasive, found in everything from mobile phones and televisions, to cars and airplanes. In order to continue to produce new and more-capable electronics, it is necessary to develop techniques for creating example electronic systems that provides critical information about how to improve the design and fabrication of integrated circuits. This NSF-funded project is focused on developing a design approach for creating integrated circuits that closely resemble electronics actually used in phones, televisions, etc. but also have the property that they can be easily diagnosed when they fail to work properly due to non-idealities in design and/or manufacturing. The knowledge learned from diagnosis will then allow the design and manufacturing to be improved in order to reduce/prevent integrated circuits for actual products (phones, cars, etc.) from failing.Under the support of the NSF program, an integrated circuit design methodology based on logic-function regularity will be developed. The planned methodology produces a test circuit that reflects various physical aspects of actual integrated circuits used in everyday products while guaranteeing optimal test and diagnosis characteristics. The methodology will allow both designers and manufacturers of integrated circuits to produce new, more capable integrated electronics for future products. Example circuits will be design and manufactured in collaboration with industrial partners to demonstrate the capabilities of the methodology.