SHF: Small: Design-for-Debug Architecture for Post-Silicon Security Validation

从智能家居中的简单电子设备到飞机上复杂的导航系统，片上系统（SoC）是各种系统中计算和通信的大脑。目前的soc设计使用硬件组件，通常是从不可信的第三方供应商那里收集的，以满足成本和上市时间的限制。这些硬件组件可能存在漏洞，攻击者可以利用这些漏洞泄露机密信息或导致系统故障。虽然研究人员提出了许多有前途的想法来检测前硅漏洞，但现有的解决方案对制造芯片（称为“后硅”阶段）并不有用，因为不可能观察或分析所有内部信号。此外，由于运行时和其他限制，在制造和/或验证期间（在“预硅”阶段）检测各种各样的漏洞是不可行的。后硅安全验证将实现安全可靠的系统。该项目的影响是通过硅前验证与硅后安全验证的协同集成来开发高度安全的soc，与行业密切合作以实现技术转让并产生具有实际意义的结果，并为劳动力培养不同背景的学生。拟议项目的主要目标是开发自动化工具和技术，使用基于模拟的安全验证和侧信道分析的有效组合来检测后硅安全漏洞。具体来说，该项目将开发一个全面的SoC漏洞列表，并设计一个完全自动化和经济高效的机制来监控运行时安全威胁。为了提高成品芯片的可观察性，该项目将开发一种有效的设计调试架构。该项目还将利用侧信道分析进行漏洞检测。该项目的成功实施有望大大减少整体SoC安全验证工作。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

System-on-Chip (SoC) is the brain behind computing and communication in a wide variety of systems, starting from simple electronic devices in smart homes to complex navigation systems in airplanes. SoCs are designed today using hardware components, often gathered from untrusted third-party vendors, to meet cost and time-to-market constraints. These hardware components may have vulnerabilities, which an attacker can exploit to leak secret information or cause system malfunction. While researchers have proposed many promising ideas to detect pre-silicon vulnerabilities, the existing solutions are not useful for fabricated chips (referred to as "post-silicon" stage), since it is not possible to observe or analyze all the internal signals. Moreover, it is infeasible to detect a wide variety of vulnerabilities during fabrication and/or validation (at the "pre-silicon" stages) due to runtime and other constraints. Post-silicon security validation will enable secure and trustworthy systems. The impacts of this project are to develop highly secure SoCs through synergistic integration of pre-silicon verification with post-silicon security validation, working closely with industry to enable technology transfer and produce results with practical significance, and training students of diverse backgrounds for the workforce.The primary objective of the proposed project is to develop automated tools and techniques to detect post-silicon security vulnerabilities using an effective combination of simulation-based security validation and side-channel analysis. Specifically, the project will develop a comprehensive list of SoC vulnerabilities, and design a fully automated and cost-effective mechanism for monitoring of runtime security threats. In order to improve the observability in fabricated chips, the project will develop an effective design-for-debug architecture. The project will also utilize side-channel analysis for vulnerability detection. A successful implementation of this project is expected to drastically reduce the overall SoC security validation effort.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.