SaTC: CORE: Small: Language Abstractions for Reconfigurable Hardware Monitors on Manycore Architectures

当攻击者利用预先存在的软件缺陷来控制程序行为时，嵌入式系统的安全性就会受到损害。即使在嵌入式硬件上运行的软件是可信的，攻击者仍然可以在程序运行时插入恶意代码，从而危及系统安全性。因此，为了减轻对嵌入式系统的此类软件攻击，将硬件和软件整体结合到一个有效的系统架构中以保护和维护我们国家的利益是至关重要的。本项目将系统、全面地探索在可重构硬件上实现高保证的动态安全策略，显著降低功耗和延迟。该研究项目将在多个领域培养新的研究方向，包括编程语言、安全策略、计算机体系结构、可重构硬件和应用，具有显著改变下一代嵌入式多核体系结构设计的潜力。所有的研究成果和模拟工具包将通过会议和期刊出版物以及一个专门的网站向社区传播。这项研究还将通过将发现与教学和培训结合起来，在教育方面发挥重要作用。该项目将继续扩大外联活动，并通过作出必要努力，吸引和培训这一领域的少数民族学生，扩大对计算机的参与。在这个项目中提出了用于规范、验证和实现可重构硬件监视器的高级语言抽象的设计和实现，特别强调对控制和信息流攻击的低开销防御。这个项目的总体目标是根据程序行为动态更新硬件，以便以最小的开销（功率、面积和时间）监视精确的安全策略。首先，该项目将开发用于实现动态安全监视器的高级语言抽象，这些监视器将在运行时重新配置以强制执行精确的安全属性。为了提供高的保证，将开发一个经过验证的编译器，用于理想化的硬件描述语言，以及相关的工具，如经过验证的方程理论。其次，这个项目将探索可重用硬件组件的设计和实现，在单核和多核环境中，高级语言抽象可以被编译。基本构建块将聚合成粗粒度可重构阵列（CGRA），可以通过状态和拓扑重构来定制程序行为。第三，在软件方面，该项目将验证安全监视器，实现对代码和控制流注入攻击的防御。在硬件方面，该项目将使用仿真工具对安全监视器进行广泛的建模和模拟，以评估基准套件的延迟、执行时间、功耗和面积开销。最后，本项目将验证由高级安全策略生成的建议硬件监视器将检测并减轻攻击。该项目将导致(1)在可重构硬件上实现动态安全策略的新颖高级语言抽象；(2)一种经过验证的理想化硬件描述语言的编译器，以及一个方程理论；(3)可重用硬件组件（基本块）的设计和实现，在允许策略重构的同时保留状态；(4)将基本块聚合到CGRA中，CGRA可以通过单核和多核架构的状态和拓扑更新来定制程序行为；(5)使用基准和工具对硬件监视器进行广泛的建模和仿真，以实现对代码和控制流注入攻击的防御。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Embedded system security is compromised when an attack exploits pre-existing software flaws in order to gain control of program behavior. Even when the software running on embedded hardware is trusted, an attacker can still insert malicious code when the program is running to compromise system security. Therefore, to mitigate such software attacks on embedded systems, it is critical that both hardware and software are holistically combined into an effective system architecture to safeguard and preserve our nation’s interests. This project will systematically and comprehensively explore the implementation of dynamic security policies with high assurance on reconfigurable hardware with significant reduction in power and latency. This research project will foster new research directions in several areas, spanning programming languages, security policies, computer architecture, reconfigurable hardware and applications, with the potential to significantly transform the design of next-generation embedded manycore architectures. All the research findings and simulation toolkits will be disseminated to the community via conference and journal publications, and a dedicated website. The research will also play a major role in education by integrating discovery with teaching and training. This project will continue to expand outreach activities and broaden participation in computing by making the necessary efforts to attract and train minority students in this field. The design and implementation of high-level language abstractions for specification, verification, and implementation of reconfigurable hardware monitors, with specific emphasis on low-overhead defenses against control- and information-flow attacks is proposed in this project. The overarching goal of this project is to dynamically update hardware in response to program behavior in order to monitor precise security policies with minimal overhead (power, area, time). First, this project will develop high-level language abstractions for implementing dynamic security monitors, those that reconfigure at runtime to enforce precise security properties. To provide high assurance, a verified compiler to an idealized hardware description language together with associated tools such as a verified equational theory will be developed. Second, this project will explore the design and implementation of reusable hardware components against which the high-level language abstractions can be compiled both in uni- and manycore environments. The basic building blocks will be aggregated into coarse-grain reconfigurable arrays (CGRA) that can be tailored to program behavior via state and topology reconfiguration. Third, in software, this project will validate security monitors implementing defenses against code- and control-flow injection attacks, among others. In hardware, this project will extensively model and simulate security monitors using simulation tools to evaluate latency, execution time, power and area overhead on benchmark suites. Finally, this project will validate that the proposed hardware monitors that are generated by the high-level security policies will detect and mitigate attacks. This project will result in (1) novel high-level language abstractions for dynamic security policies implemented on reconfigurable hardware; (2) a verified compiler to an idealized hardware description language together with an equational theory; (3) the design and implementation of reusable hardware components (a basic block) that retain state while allowing policy reconfiguration; (4) the aggregation of basic blocks into CGRA that can be tailored to program behavior via state and topology updates for uni- and manycore architectures; and (5) extensive modeling and simulation of hardware monitors that implement defenses against code- and control-flow injection attacks using benchmarks and tools.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.