SHF: Small: Leveraging Monolithic 3D for Architectural Innovations

设计更高效的处理器是计算行业的主要推动力。几十年来，缩小晶体管的尺寸一直是效率提高的主要驱动力。晶体管是微处理器的组成部分。随着晶体管缩小到接近物理极限的趋势，这项研究探索了三维芯片，其中晶体管堆叠在多层中，作为提高效率的替代方法。三维芯片的一个主要挑战是，与晶体管本身相比，连接的尺寸很大。该项目将利用一种名为单片三维设计(M3D)的新技术，其中层间连接的尺寸类似于晶体管的尺寸。这项研究将产生新的基于M3D的微处理器设计，减少互连中的能量和时间消耗，并使微处理器具有新的功能特征。该项目还将通过在急需的半导体电子领域培训本科生、研究生和代表性不足的群体，加强全国劳动力发展努力。该项目将涉及协同探索工艺技术和基于M3D的处理器架构设计空间，以实现对处理器和加速器性能的转型影响。这项研究将首先开发一个模拟基础设施，通过改变建筑和技术参数来实现对空间的系统探索。利用模拟基础设施，该项目将执行以下任务：(1)评估处理器核心和高速缓存结构的分层分区；(2)设计与高速缓存存储器集成的基本计算功能；(3)设计支持M3D的特定应用程序加速器；以及(4)集成不同的内存技术，以提供对能源效率的支持。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

The design of more efficient processors is a major driving force of the computing industry. Over multiple decades, reducing the size of transistors, which are the building blocks of microprocessors, has been the main driver for efficiency improvements. With this trend of transistor shrinking nearing the physical limit, this research explores three-dimensional chips, where transistors are stacked in multiple layers, as an alternate approach to enhance efficiency. A major challenge with three-dimensional chips is the large dimension of the connections compared to the transistor itself. This project will leverage a new technology called monolithic three-dimensional design (M3D), where inter-layer connections are of dimensions similar to that of a transistor. This research will result in new M3D-based designs for microprocessors that reduce energy and time consumed in interconnections, and enable new functional features for microprocessors. The project will also enhance the national workforce development efforts by training undergraduate, graduate and underrepresented groups in a much-needed area of semiconductor electronics. This project will involve synergistic exploration of process technology and M3D-based architectural design spaces of processors towards achieving transformational impact on processor and accelerator performance. The research will first develop a simulation infrastructure that enables systematic exploration of the space by varying the architectural and technology parameters. Leveraging the simulation infrastructure, this project will perform the following tasks: (1) evaluation of layer-wise partitioning of processor core and cache structures; (2) design of primitive compute functions for integration with the cache memories; (3) design of M3D-enabled application-specific accelerators; and (4) integration of heterogeneous memory technologies to provide support for power efficiency.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.