Design of efficient 3D integrated DRAM subsystem architectures based on detailed designspace explorations and modeling

微电子系统3D集成领域的进步使得单个封装中的IC的可靠和成本效益的密度增加成为可能。通过集成具有非常高通信带宽的可扩展3D集成DRAM和相应的逻辑（例如存储器控制器），将具有不同技术和功能的异构IC紧密集成的可能性为“存储器/处理器差距”开辟了一条出路。通过这种方式，标准DRAM与MPSoC的3D集成可以大大提高能量效率，增加存储带宽.然而，这只是MPSoC的内存子系统的一个完整的修订的起点，考虑到3D集成的新可能性。即DRAM架构，其接口和存储器控制器必须彻底重新研究，以实现更高的带宽，更好的能源效率，更低的系统延迟，更高的存储器封装密度和更大的可扩展性相比，国家的最先进的架构。然而，这种3D-DRAM子系统的设计空间非常大，因为它覆盖了3D-DRAM立方体、接口和存储器控制器。这个设计空间必须系统地探索与适当的指标，以获得最佳的配置参数。据我们所知，没有研究或出版物来优化3D-DRAM，接口和控制器。因此，本提案的目标是内存控制器、接口和3D-DRAM立方体的共同优化，特别是为了满足计算约束和要求。

The progress in the field of 3D integration of microelectronic systems enables a dependable and costeffective density increase of ICs in a single package. The possibility to closely integrateheterogeneous ICs with different technologies and functionalities opens a way out of the"Memory/Processor Gap" via integration of scalable 3D integrated DRAMs with very highcommunication bandwidths and the corresponding logic (e.g. memory controller). In this way 3Dintegration of standard DRAMs with MPSoCs can largely improve the energy efficiency and increasethe memory bandwidth. However, this is only the starting point for a complete revision of the memorysubsystem of MPSoCs considering the new possibilities of 3D integration. I.e. DRAM architectures,their interfaces and memory controllers have to be thoroughly reinvestigated to achieve higherbandwidth, better energy efficiency, lower system latency, higher memory packing density and largerscalability compared to the state-of-the-art architectures. However, the design space for such a 3D-DRAMsubsystem is very large, since it covers the 3D-DRAM cube, the interfaces and the memorycontroller. This design space has to be systematically explored with appropriate metrics to obtain theoptimum configuration parameters. To the best of our knowledge there are no investigations orpublications to optimize 3D-DRAM, interfaces and controller jointly. Hence, the objective for thisproposal is the co-optimization of memory controller, interfaces and 3D-DRAM cube especially tomobile computing constraints and requirements.