1-D Multi-Gate FETs: Tailoring the Potential Landscape on the Nanoscale

近年来，纳米线和纳米管等一维材料作为未来纳米电子系统的构建块引起了人们极大的关注。这种兴趣部分归因于小的几何结构，由于在例如缠绕栅极器件结构中的强大的静电栅极控制，其允许实现器件的最佳可伸缩性。此外，纳米线/管实现了一维电子传输，其具有许多优点，例如用于散射的相当长的平均自由程或高度线性的传输特性。此外，1-D传输和出色的栅极控制相结合，能够严格控制器件内的潜在分布。虽然使用栅极来操纵基于新材料的晶体管器件的电位分布是常见的做法，但到目前为止只使用了少量的栅极，并且这些栅极呈现出几十到数百纳米量级的长度和/或彼此相距很远，从而禁止在纳米尺度上操纵电位分布。本方案的目的是实现一维多栅极器件体系结构，其中大量长度在几纳米范围内的栅极(大约10个数量级或更多)将以几纳米的栅间距离彼此相邻放置。由于一维纳米结构出色的栅极控制，这种器件布局允许在纳米尺度上沿着器件定制导带/价带分布；因此，这种能带定制允许研究一维结构在纳米电子学中的全部潜力。该项目将进行两个不同的演示：第一，将在例如碳纳米管和/或InAs纳米线中实现栅感应超晶格结构。在适当的尺寸下，这种超晶格将充当能量过滤器，使所谓的陡坡晶体管能够在非常低的电源电压下运行，从而促进超低功率纳米电子系统的发展。其次，我们将沿通道调整频带分布，以最大化一维器件传输特性的线性度。

One-dimensional (1-D) materials such as nanowires and nanotubes have attracted a great deal of attention recently as buildings blocks of future nanoelectronics systems. This interest is in part due to the small geometry that allows realizing optimum scalability of the devices due to the strong electrostatic gate control in e.g. wrap-gate device structures. In addition, nanowires/tubes enable one-dimensional electronic transport that has a number of benefits such as a rather long mean free path for scattering or the highly linear transfer characteristics. Furthermore, the combination of 1-D transport and excellent gate control enables a tight control over the potential distribution within the device. While it is common practice to use gates in order to manipulate the potential profile of transistor device based on novel materials so far only a small number of gates has been used and these gates exhibit a length on the order of several tens to hundreds of nanometers and/or are placed far apart from each other prohibiting a manipulation of the potential profile on the nanoscale. The aim of the present proposal is to realize a 1-D multi-gate device architecture where a large number of gates (on the order of 10 and more) with lengths in the few nanometer range will be placed next to each other with a few nanometers inter-gate distances. This device layout allows tailoring the conduction/valence band profile along the device on the nanoscale due to the excellent gate control in 1-D nanostructures; hence this band tailoring allows studying the full potential of 1-D structures for nanoelectronics. Two different demonstrations will be pursued within the project: First, a gate-induced superlattice structure will be realized in e.g. carbon nanotubes and/or InAs nanowires. With appropriate dimensions this superlattice will serve as an energy filter enabling a so-called steep slope transistor that operates at very low supply voltages and hence facilitates ultra-low power nanoelectronics systems. Second, we will adjust the band profile along the channel in order to maximize the linearity of the transfer characteristics of the 1-D device.