Cryogenic Complementary Metal-Oxide-Semiconductor Technology for the Realization of Classical QuBit-Control Circuits

量子信息技术有望释放出巨大的计算能力，解决当今经典计算机难以解决的问题。然而，一个有用的量子信息处理器（QIP）的实现将涉及大量的耦合量子比特。这样做的原因是每个逻辑量子位由大量的物理量子位实现组成，以便利用表面代码建立适当的纠错。每个物理量子位都需要一个控制单元来提供读出、门脉冲和偏置参数。一个主要的挑战是，实现固态量子比特的最有希望的方法是在低温下操作，这限制了每个量子比特的可用冷却功率在微到纳瓦范围内的非常低的值。典型的实验是由位于室温或至少高于量子位的温度的外部电路控制的。由于互连性和尺寸的考虑，将这种方法扩展到所需数量的量子位似乎完全不切实际。因此，将微制造经典硬件和量子硬件紧密结合在一起的集成方法非常有吸引力。然而，将经典控制电子元件集成到接近实际量子位芯片需要控制电子元件在超低功耗水平下在~1K的温度下工作（同时执行类似于最先进的CMOS电路）。由于冷却功率有限，低温CMOS电路必须在几十毫伏的极低电源电压下工作。这意味着需要非常陡峭的逆亚阈值斜率，对阈值电压的非常严格的控制以及非常低的可变性，这是不可能通过简单地冷却现有技术来实现的，优化为室温操作。目前的提案是一个项目的延续，该项目一直致力于探索和开发一种专用的低温CMOS （cCMOS）技术，以及基于该cCMOS技术的场效应晶体管的制造和表征。在之前的项目中，我们展示了两种获得陡坡低温场效应管的有希望的方法，并研究了如何在这种器件中避免掺杂的方法。在此，我们的目标是进一步发展这些方法并将它们结合起来，以实现cCMOS陡坡器件。

Quantum information technology holds promise to unleash enormous computational power to solve problems that are intractable on today's classical computers. However, the realization of a useful quantum information processor (QIP) will involve a large number of coupled qubits. The reason for this is that each logic qubit consists of a large number of physical qubit implementations in order to establish an appropriate error correction utilizing e.g. surface codes. Each of the physical qubits requires a control unit that provides readout, gate pulses and bias parameters. One major challenge is that the most promising approaches for the realization of solid-state qubits are operated at cryogenic temperatures, which limits the available cooling power per qubit to very low values in the micro- to nanowatt regime. Typical experiments are controlled by external circuits located at room temperature, or at least at a temperature higher than that of the qubit. Extending this approach to the required number of qubits appears completely unpractical because of interconnectivity and size considerations. An integrated approach with microfabricated classical and quantum hardware in close proximity is thus very attractive. However, integrating classical control electronics close to the actual qubit chip requires the control electronics to be operated at a temperature of ~1K (while performing similar to state-of-the-art CMOS circuits) at an ultra-low power level. As a result of the limited cooling power, cryogenic CMOS circuits have to be operated at very low supply voltage in the tens of mV regime. This implies that extremely steep inverse subthreshold slopes, a very tight control of the threshold voltage as well as very low variability are required which is impossible to be achieved by simply cooling down the existing technology, optimized for room-temperature operation. The present proposal is a continuation of a project that has been targeting the exploration and development of a dedicated, cryogenic CMOS (cCMOS) technology and the fabrication and characterization of field-effect transistors based on this cCMOS technology. Within the preceding project we were able to show two promising ways to obtain steep slope cryogenic FETs and studied ways how to avoid dopants in such devices. Here, we aim at further developing the approaches and combining them in order to realize cCMOS steep slope devices.