课题基金 / 基金详情

Research on Development of High-Speed Logic Simulators Using a Vector Processor and Logic Design Verification Systems

Research on Development of High-Speed Logic Simulators Using a Vector Processor and Logic Design Verification Systems
使用矢量处理器和逻辑设计验证系统的高速逻辑模拟器的开发研究
批准号:
61850062
负责人:
YAJIMA Shuzo
金额:
$4.67万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Developmental Scientific Research
财政年份:
1986
资助国家:
日本
项目状态:
已结题
起止时间:
1986 至 1987

项目摘要

项目成果

YAJIMA Shuzo的其他基金

相似基金

相关文献

中文摘要
翻译
为了实现大规模逻辑系统的高可靠性设计,必须建立严格的设计验证方法和有效的支持系统。从这一角度出发,我们开展了基于向量处理器的高速逻辑模拟器的开发和逻辑设计验证系统的研究。其主要结果如下所示。使用向量处理器的高速逻辑仿真器我们开发了适用于向量处理的仿真算法,并实现了仿真器。对于零延迟二值逻辑模拟,我们获得了每秒7.7x10^9门评估(组合电路)和1.4x10^9门评估每秒(时序电路)的非常高的性能。对于一个可分配延迟的四值逻辑模拟,实现了每秒3.4×10^5个事件。逻辑设计验证系统我们给出了表达等价于正则集的正则时序逻辑(RTL)的可满足性判定问题和模型检验的算法。基于这些结果,我们建立了使用RTL的设计验证方法。我们还开发了一种使用#-Expression的时序验证方法,它是正则表达式的扩展。为了准确、快速地显示大量信息,我们开发了一种基于多机多屏方法的工作站,它可以超越单屏和并行高速绘图的限制,实现高分辨率显示。
英文摘要
For a highly reliable design of large scale logic systems, it is essential to establish rigid methodologies and efficient support systems for design verificaion. From this point of view, we habe performed researches on development of high-speed logic simulators using a vector processor and logic design verification systems. Theis main results are listed below.1. High-Speed Logic Simulators Using a Vector Processor We have developed simulation algorithms suitable for vector processing and implemented the simulators. For a zero-delay two-valued logic simulation, we have achived very high speed performance of 7.7x10^9 gate evaluation per second(combinational circuits) and 1.4x10^9 gate evaluation per second (sequential circuits). For a assignable-delay four-valued logic simulation,3.4x10^5 event per second have been achieved.2. Logic Design Verification SystemsWe have deceloped algorithms for decision problems of satisfiability and model checking of Regular Temporal Logic(RTL) which is expressively equivalent to the regular set. Based on these results, we have established design verification methods using the RTL. We have alse developed a timing verification method using #-expression, which is an extension of the regular expression.3. Workstation for Logic DesignIn order to display a large amount of information precisely and quikly, we have developed a workstation based on a multi-computer multi-screen method, which enables high-resolution display beyond the limit of a single screen and parallel high-speed drawign.
期刊论文(28)
专著(0)
科研奖励(0)
会议论文
Nagisa Ishiura: Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD-87). 10-13 (1987)
Nagisa Ishiura:IEEE 国际计算机辅助设计会议 (ICCAD-87) 论文集。
DOI: --
发表时间:
期刊:
影响因子: --
作者: []
通讯作者:
Shigeharu Teshima: "Algebric Specification of Paralle Systems Based on Binary Relations between Events" Transactions of the Institute of Electronics,Information and %communication Engineers. J70-D. 19-29 (1987)
Shigeharu%20Teshima:%20"代数%20规格%20of%20Paralle%20Systems%20Based%20on%20Binary%20Relations%20Between%20Events"%20Transactions%20of%20the%20Institute%20of%20电子、信息%20和%20%communication%
DOI: --
发表时间:
期刊:
影响因子: --
作者: []
通讯作者:
DOI: --
发表时间:
期刊:
影响因子: --
作者: []
通讯作者:
DOI: --
发表时间:
期刊:
影响因子: --
作者: []
通讯作者:
共 24 条
    Research on Development of Formal Logic Design Verifier for Microprocessors
    • 批准号:
      07558155
    • 项目类别:
      Grant-in-Aid for Scientific Research (A)
    • 资助金额:
      $1.41万
    • 财政年份:
      1995
    • 负责人:
      YAJIMA Shuzo
    • 依托单位:
    Basic Research on High-Speed Boolean Function Manipulator
    • 批准号:
      05452352
    • 项目类别:
      Grant-in-Aid for General Scientific Research (B)
    • 资助金额:
      $4.35万
    • 财政年份:
      1993
    • 负责人:
      YAJIMA Shuzo
    • 依托单位:
    Research on Formal Verifier of Logic Design Based on Temporal Logic
    • 批准号:
      05558030
    • 项目类别:
      Grant-in-Aid for Developmental Scientific Research (B)
    • 资助金额:
      $6.85万
    • 财政年份:
      1993
    • 负责人:
      YAJIMA Shuzo
    • 依托单位:
    Research on Development of Logic Synthesizer and Design Verifier for Sequential Circuits Based on Boolean Function Manipulation
    • 批准号:
      03555074
    • 项目类别:
      Grant-in-Aid for Developmental Scientific Research (B)
    • 资助金额:
      $5.31万
    • 财政年份:
      1991
    • 负责人:
      YAJIMA Shuzo
    • 依托单位:
    海外基金