Study on Architecture and Design Methdology of Asynchronous Processors

1)基于寄存器传输和算术运算等原子操作之间的依赖关系，提出了一种高效的异步控制电路综合方法。在这种方法中，描述电路行为的依赖图直接映射到原始电路元件之间互连的描述。2)设计了一种准延迟不敏感的通用8位微处理器芯片TITAC，并将其实现为CMOS门阵列。TITAC项目旨在证明在实践中工作的完全异步VLSI系统的设计方法是现成的。通过TITAC的设计与实现，我们建立了异步VLSI系统设计自动化的构建模块库。3)分析了准延迟不敏感电路中导致信号非法转换的卡滞故障，提出了一种增强信号转换可控性和可观察性的可测试性设计。4)我们首先将自定时实现的转换因果关系定义为主要输入、主要输出和内部门上的信号转换之间的一组因果关系，并提出了一种新的布尔函数的自定时实现。由此产生的电路实现了最大的并行性，因此，具有在延迟不敏感电路环境模型上以最高可能的平均速度运行的潜力。5)我们开发了一种使用约瑟夫森结器件实现的脉冲驱动异步电路的栅极模型和电路结构，其中二进制信息由极短的电压脉冲表示。

1) We developed an efficient synthesis method for asynchronous control circuits based on dependency relations between atomic operations such as register transfers and arithmetic operations. In this method, a dependency graph which describes a circuit behavior is directly mapped to a description of the interconnection among primitive circuit elements.2) We designed a quasi-delay-insensitive general-purpose 8-bit microprocessor chip TITAC,and implemented it as a CMOS gate array. The TITAC project seeks to demonstrate that a design methodology is readily available for fully asynchronous VLSI systems that work in practice. Through the design and implementation of TITAC,we established a library of building blocks for the design automation of asynchronous VLSI systems.3) We analized stuck-at faults that cause illegal signal transitions in quasi-delay-insensitive ccircuits, and proposed a design for testability by enhancing the controllability and observability of signal transitions.4) We first defined the transition causality of a self-timed implementation as a set of causal relations that hold among signal transitions on the primary input, primary output and the internal gates, and proposed a new self-timed implementation of Boolean functions. The resulting circuit achieves a maximum parallelism, and consequently, has a potential of operating at a highest possible average speed on the delay-insensitive circuit-environment model.5) We developed a gate model and circuit structure for pulse-driven asynchronous circuits implemented with the use of Josephson junction devices, in which the binary information is presented by very short voltage pulses.