New Architecture Microprocessor Based on High-Density Distributed Placement of Memory-Function-Merged Processing Units

本文研究了用一种完全不同于冯·诺依曼型微处理器的“新硬件”体系结构实现灵活、实时响应的智能系统的基本技术。在“新硬件“中，通过存储器功能合并的实时可重构处理单元的分布式布局和有效的网络化，实现了无瓶颈的理想数据流，从而实现了实时响应。具有实时可重构性的“flexware“可以通过使用高功能性四端器件，即神经元MOS晶体管（vMOS），用非常少的元件来构建。采用vMOS设计，成功地设计了一种用于微处理器超高速自定时操作的握手电路，其元件数比CMOS设计少。新开发的“时钟-vMOS”电路方案，其中时钟控制开关附加到vMOS的浮栅，提高了精度， ...更多信息 这种新的电路技术融合了开关电容技术和vMOS技术，使减法功能可以直接在vMOS浮栅上实现。应用灵敏放大器技术，提出了一种适用于vMOS器件的低功耗电路方案。结合这些新技术，我们研制出了低功耗A/D转换器和高速乘法器电路。所研制的4-B Flash A/D转换器测试电路在6 MS/s采样频率下功耗仅为1.2mW，功耗小于传统A/D转换器的1/10。我们通过模拟表明，具有新开发的闪存求和机制的64-B乘法器可以工作在3 ns的吞吐量。研究了实现高功能vMOS电路所需的工艺精度。在vMOS电路中处理50阶多值变量时，要求器件的主要结构参数具有极少量的精度。少

We have studied the fundamental technologies to realize flexible and real-time response intelligent systems by a "New Hardware" architecture, which completely differs from Von Neumann type microprocessors. In the "New Hardware, "a bottle-neck-free ideal data flowing can be achieved by the distributed placement of memory-function-merged real-time-reconfigurable processing units and by an effective networking of them, resulting in the realization of real-time response. The "flexware, " which has a real-time reconfigurability, can be constructed with a very small number of elements by using high-functionality four-terminal devices, namely, Neuron-MOS transistors (vMOS). An hand-shake circuit for ultra-high speed self-timed operation of microprocessors has been successively designed using vMOS design with fewer elements than CMOS design. The newly developed "Clocked-vMOS" circuit scheme, in which a clock-controlled switch is attached to the floating gate of vMOS,increases the accuracy and … More the reliability of the circuits and also allows the realization of the subtraction function directly on the floating gate of vMOS.This new circuit technology merges the switched-capacitor technology and the vMOS technology. Low power circuit scheme for vMOS has been developed by applying the sense-amplifier technology. By combining all these new technologies, we have developed a low power A/D converter and a high speed multiplier circuit. The fabricated 4-b flash A/D converter test circuit only dissipates 1.2mW at the sampling frequency of 6MS/s, reducing the power consumption to less than 1/10 of the conventional A/D converters. We have shown by simulation that the 64-b multiplier having the newly-developed flash-summation mechanism can operate at the throughput of 3ns. The fabrication process accuracy required to realize high-functionality vMOS circuits were studied. Accuracy of the order of few percents is required for the main structural parameters of the device when it is aimed to handle 50-level multiple-valued variable in vMOS circuits. Less