Coupled Hybrid Bandwidth Peaking Techniques for BiCMOS Multiplexer and Demultiplexer Beyond 200 Gb/s (PEAK)

未来将需要运行超过100 GB/S的通信系统。为了实现这样的超高数据速率，可以使用多路复用器(MUX)和多路分解器(DMUX)电路以较低的速度将数据分割成多个并行流。在BiCMOS中，发布了数据速率高达180 Gb/S的多路复用器IC和高达100 Gb/S的多路复用器IC。为了达到最大速度，需要使用感应带宽峰值技术。最常用的是串联式、分联式或T型线圈的峰化方法，它们能够将带宽分别提高1.4倍、1.7倍和2.8倍。匹克希望将BiCMOS多路复用器和多路复用器的技术水平推到200 GB/S以上。将包括用于同步的锁存器。T形线圈主要使用提供远低于200 GHz的自谐振频率(SRF)的耦合螺旋电感来实现。因此，它们不适合巅峰。我们研究了能够工作在200 GHz以上的新型传输线T型线圈。T形线圈的峰值利用了强相互线圈耦合。然而，在200 GHz附近，耦合线路的长度与线路距离之比很低。这会导致较小的耦合系数，从而降低峰化效率。我们想要研究如何在保持高SRF的同时最大化线圈耦合。此外，我们还研究了如何优化具有中等T线圈耦合的IC，例如，通过增加极点以及巧妙地与串联和/或并联峰化相结合。通过在级联电路块的输入、中间和输出节点上智能分布异类的峰化方法，扩展了这些高阶峰化方法。为了更深入地理解势能和极限，推导了方程。除了带宽，我们还研究了与阶跃响应、时钟和数据信号的抖动以及群延迟有关的权衡，以最终实现大开眼界。包装上的寄生因素也会被考虑在内。可选地，我们还研究了多相体系结构以放松锁存的速度。为了验证这些方法，多路复用器和多路复用器演示IC采用最快的IHP BiCMOS工艺实现。我们的初步模拟预测，多路复用器和多路复用器的速度应该可以超过200 GB/S。这些电路将用于两个应用：第一，作为更快通信系统的使能器，第二，扩展我们更多的测量平台，可以由第三方用户评估。更多包括，例如，我们最先进的SHF误码率测试仪(BERT)，即使在非归零(NRZ)调制下，它也能够测量高达每条路径120 Gb/S的电路。通过使用峰值多路复用器和多路复用器的两条路径，我们可以将More-BERT扩展到每条路径200 GB/S的创纪录速度。这也将有利于由来自6所德国大学的12名教席组成的更多合作伙伴。因此，匹克增强了德国研究团体设计最快集成电路的能力。

Communication systems operating beyond 100 Gb/s will be required in the future. To enable such ultra-high data rates, the data can be split in multiple parallel streams with lower speed using multiplexer (MUX) and demultiplexer (DMUX) circuits. In BiCMOS, MUX ICs with data rates up to 180 Gb/s and DMUX ICs up to 100 Gb/s were published. To reach maximum speeds, inductive bandwidth peaking techniques are required. Most frequently, series, shunt or T-coil peaking approaches are applied, which are capable to improve the bandwidth by factors up to 1.4, 1.7 and 2.8, respectively. PEAK wants to push the state of the art of MUX and DMUX in BiCMOS beyond 200 Gb/s. Latches for synchronisation will be included. T-coils are mainly realised using coupled spiral inductors providing self-resonance frequencies (SRFs) well below 200 GHz. Hence, they are not suited for PEAK. We investigate novel transmission-line-based T-coils capable to operate well beyond 200 GHz. T-coil peaking exploits strong mutual coil coupling. However, around 200 GHz, the ratio between the length of the coupled lines and the line distances is low. This leads to smaller coupling factors and hence less efficient peaking. We want to investigate how the coil coupling can be maximised while keeping the SRFs high. Furthermore, we study how ICs with moderate T-coil coupling can be optimised, e.g. by adding of poles and smart combination with series and/or shunt peaking. These higher order peaking methods are extended by smart distribution of heterogeneous peaking approaches at the input, intermediate and output nodes of cascaded circuit blocks. To deeply understand the potentials and limits, equations are derived. In addition to the bandwidth, we investigate also trade-offs with respect to the step response, jitter of the clock and data signals and group delay, to finally allow large eye-openings. The packaging parasitics will be taken into account. Optionally, we investigate also multi-phase architectures to relax the speed of the latches. To verify the approaches, MUX and DMUX demonstrator ICs are realised in the fastest IHP BiCMOS technology. Our preliminary simulations predict that MUX and DMUX speeds beyond 200 Gb/s should be possible. The circuits will be applied for 2 applications: First, as enabler for faster communication systems, and second, to extend our MORE measurement platform, which can be assessed by third party users. MORE includes e.g. our state-of-the-art SHF bit-error-rate-tester (BERT), which is capable to measure circuits up to 120 Gb/s per path even with non-return-to-zero (NRZ) modulation. By applying two paths using the PEAK MUX and DMUX, we can extend the MORE-BERT towards a record speed of 200 Gb/s per path. This will also be beneficial for the MORE partners consisting of 12 chairs from 6 German universities. Hence, PEAK strengthens the German research community to design fastest ICs.