Mixed-Signal Electronics and Digital Signal Processing for Energy-Efficient Wireless Communication above 100Gbps (MEDSEEC-100)

启用太比特无线通信系统意味着使用25-50 GHz的非常大的信道带宽，这在100 GHz以上的亚太赫兹频率范围内可用。数据速率约为100Gbit/S的无线通信的一个主要挑战是接收器设计。特别是在高采样率下，模数转换器(ADC)成为了一个主要的能源消耗瓶颈，与经典的多位量化相比，具有显著过采样的1位量化可以成为一种节能的方法。可实现的功耗节约源于对接收器的更宽松的线性度要求、对自动增益控制的有限需求以及更简单的ADC架构的应用。此外，具有过采样的1比特量化对于具有较小电压范围但允许高时间分辨率的纳米级半导体工艺是完美匹配的(例如，GlobalFoundries过程22FDX工作在0.4-0.8V，最大振荡频率Fmax≈370 GHz)。在我们先前的工作中，我们已经研究了基于过采样1比特量化的这种太比特无线通信系统的几个组件。我们开发了一种自适应的调制和信令方案，无线电前端组件为200 GHz左右的载波频率提供了足够的带宽，以及用于时间过采样1比特量化的电路。此外，我们还推导了信道参数估计和首次估计算法的基本限制。基于这些结果，我们想要研究使用1比特量化实现高能效混合信号电子和数字信号处理接收机的关键设计方面。其目的是了解模拟硬件的能效和通信性能之间的权衡。由于接收机的一个关键方面是信道参数估计，我们希望找到适合于使用1比特量化的接收机的参数估计目标函数，然后系统地从中推导出实用的定时估计器。此外，我们还将研究模拟前端失真和采样抖动对通信性能的影响。为了在不同速率要求的情况下实现高能效，我们进一步研究了两种并行方法的最小功耗的1位ADC电路。首先，改进我们以前在200Gbit/S采样率下的结果，ADC的核心模块将引入新的自适应能力，实现采样率的精确控制，优化功耗，并实现工艺和温度变化的自动补偿。其次，这些电路将被设计为非常快速地切换，当只需要以峰值速率传输短突发数据时，能够进一步降低功耗。为了进一步提高硬件的效率，我们将采用先进的22 nm FD-SOI CMOS工艺实现电路。

Enabling terabit wireless communication systems implies the use of very large channel bandwidths of 25-50 GHz, which are available in the subterahertz frequency range beyond 100 GHz. A major challenge for wireless communication with data rates in the order of 100 Gbit/s is the receiver design. In particular, at the necessarily high sampling rates, the analog-to-digital converters (ADCs) become a major energy consumption bottleneck.In contrast to classical multi-bit quantization, 1-bit quantization with significant oversampling can be an alternative energy-efficient approach. The achievable power savings result from more relaxed linearity requirements on the receiver, limited need of automatic gain control, and the application of simpler ADC architectures. Moreover, 1-bit quantization with oversampling is a perfect match for nm-scale semiconductor processes that have a decreased voltage range but allow for a high time resolution (e.g., the GlobalFoundries process 22FDX operates at 0.4-0.8 V with a maximum frequency of oscillation fmax ≈ 370 GHz).In our previous work we have already studied several components of such terabit wireless communication systems based on oversampled 1-bit quantization. We developed an adapted modulation and signaling scheme, radio frontend components providing sufficient bandwidth for carrier frequencies around 200GHz, and circuits for temporally oversampled 1-bit quantization. Moreover, we derived fundamental limits on channel parameter estimation and first estimation algorithms. Based on these results, we want to study key design aspects of the realization of energy-efficient mixed signal electronics and digital signal processing for receivers using 1-bit quantization. The aim is to understand the trade-offs between energy efficiency of the analog hardware and the communication performance. Since a key aspect of a receiver is channel parameter estimation, we want to find parameter estimation objective functions that are suitable for receivers that use 1-bit quantization, from which we then systematically derive practical timing estimators. Moreover, we will study the impact of distortions by the analog frontend and sampling jitter on the communication performance. To achieve high energy efficiency in case of varying rate requirements, we further study circuits for 1-bit ADC of minimum power consumption with two concurrent approaches. First, improving our previous results at sampling rates of 200Gbit/s, the core blocks of the ADCs will introduce novel adaptivity and enable precise control of the sampling rate, optimizing power consumption and realizing automatic compensation of process and temperature variation. Second, the circuits will be designed to be switched very rapidly, enabling further reductions in power consumption when only short bursts of data need to be transmitted at peak rate. To further improve the efficiency of the hardware, we will realize the circuits in an advanced 22 nm FD-SOI CMOS technology.