Self-Reconfigurable Massively Parallel Computer on Stacked Wafers

本文研究了一种基于堆叠晶圆的三维网格阵列及其容错结构。三维网格阵列的架构使用递归移位方案提供了互连的自重构。Anuj Chandra等人也提出了一种3D 1/ track模型的可重构算法，该算法基于s.y.k un等人最初提出的补偿路径方案。然而，对三维1/轨迹模型的讨论仅仅是从二维1/轨迹模型扩展的理论角度出发。本文研究了其容错性能，利用自重构方案获得了三维网格阵列的系统成品率。首先，我们回顾了近年来用于构建大规模并行计算机的WSI器件，并总结了WSI并行计算机的优点。下一个。我们讨论了网格连接的多处理器架构和重构策略，以提高WSI实现的阵列良率。通过与以往工作的比较，讨论了网格并联计算机的重构性能。讨论了立方体连接周期（CCC）的WSI实现，并通过考虑pe、开关和链路的芯片面积来讨论其良率性能。我们还提出了一种基于交叉立方体互连的新型互连网络HCQ，以减小互连网络的直径和平均距离。对HCQ优良的网络性能进行了理论研究。最后，我们讨论了用于大规模并行计算机的堆叠晶圆上的3d网格阵列。提出了一种基于递归移位的重构算法。将递归移位方案应用于三维网格阵列，表明重构性能提高，并为在像三维网格阵列这样的堆叠晶圆上构建大规模并行计算机提供了可能。

This research deals with a 3D-mesh array on stacked wafers and its fault tolerant architecture. The architecture of 3D-mesh arrays provides a self-reconfiguration of interconnections using a recursive shift scheme. Anuj Chandra et al. also proposed a reconfigurable algorithm for 3D 1/ track model based on a compensation path scheme that was originally proposed S.Y.Kung et al. The 3D 1/ track model was, however, discussed only from the theoretical view points of extension of the 2D 1/ track model. This paper examines its fault tolerant performance to obtain the system yield of a 3D-mesh array using a self-reconfiguration scheme.First, we reviews recent WSI devices to construct massively parallel computers and summarize the merit of WSI parallel computers. Next. we deal with the mesh-connected multiprocessor architecture and reconfiguration stategies to enhance the array yield for WSI implementation. Reconfiguration performance of a mesh-connected parallel computer is discussed by comparing it to previous works. WSI implementation of a cube-connected cycles (CCC) is addressed and its yield performance is discussed by taking into account the chip area of the PEs, switches, and links. We also propose a new interconnection network HCQ based on a crossed cube interconnection to reduce the diameter and the average distance of the interconnection network. The excellent network property of HCQ is theoretically investigated. Finally, we discussed a 3D-mesh array on stacked wafers for massively parallel computers. A reconfiguration algorithm based on a recursive shift scheme is proposed. Applying the recursive shift scheme to a 3D-mesh array, it is shown that the reconfiguration performance becomes high and provides the possibility to construct a massively parallel computer on stacked wafers like as the 3D-mesh array.