HIGH PERFORMANCE DEVICES FOR GIGASCALE INTEGRATED SYSTEMS

1.用四端器件实现高性能的大规模集成电路和千兆级集成系统我们用四端器件神经元-MOS(Neuron-MOS)作为基本器件，实现了智能电子系统的基本电路。设计、制作和评估了测试电路；利用VMOS开发了实时运动矢量检测器和实时质心跟踪电路；开发了高速高精度模拟非易失性存储器、基于曼哈顿距离计算的VMOS相关器、VMOS赢家通吃电路等智能事件识别硬件的关键部件。使用与事件识别硬件相同的体系结构，我们利用数字电路技术开发了一种用于实时运动图像压缩的矢量量化(VQ)处理器芯片。与使用微处理器…的软件实现相比，VQ芯片的速度性能高出1,000倍更多(奔腾166 MHz)。千兆级集成的低功耗器件/电路技术电路的低功耗操作是千兆级集成的关键。我们开发了两种新的VMOS低功耗电路方案。一种是将读出放大器应用于VMOS逻辑判决电路而开发的读出放大VMOS逻辑电路方案。另一种是深阈值VMOS方案，采用深阈值晶体管和有效设计的缓冲电路。研制出了即使在1V电源下也能表现出高性能的Ta栅SOI-MOSFET。为千兆级集成电路开发了超低功耗绝热逻辑电路方案。千兆级集成的限制千兆级集成的机会由物理限制的层次结构管理，该层次结构可分为五个级别：基准级、材料级、器件级、电路级和系统级。这一独特的方法通过阐明MOSFET沟道区随机掺杂原子放置对千兆积分的影响而得到扩展。系统配置的优化基于最新导出的完全随机互连分布，定义了一种最小化芯片面积和功耗的最优布线网络结构。较少

1. High Functional LSI and Gigascale Integrated System realized by four-terminal deviceWe have realized elemental circuits for an intelligent electronic system by using a four-terminal device, Neuron-MOS (vMOS), as an elemental device. Test circuits were designed, fabricated and evaluated by the measurement of fabricated test circuits.Real-time motion-vector detector and real-time center-of-mass tracer circuit have been developed by using vMOS.High-speed and high-accuracy analog non-volatile memory, vMOS correlator based on Manhattan distance computation, vMOS winner-take-all circuit, which are the key elements of intelligent event-recognition hardware, have been developed. By using the same architecture as the event-recognition hardware, we have developed a vector quantization (VQ) processor chip for real-time motion picture compression using digital circuit technology. The VQ chip exhibits 1,000 times superior speed performance compared to software realization using a microprocessor … More (Pentium 166MHz).2. Low Power Device / Circuit Technology for Gigascale IntegrationLow power operation of the circuit is essential for gigascale integration. We have developed two new low-power circuit schemes for vMOS.One is a sense-amp vMOS logic circuit scheme, which is developed by applying a sense-amplifier to the vMOS logic decision circuit. The other is a deep-threshold vMOS scheme, in which deep threshold transistors and effectively-designed buffer circuit are utilized. Ta-gate SOI-MOSFET which exhibits high performance even with a 1V power supply has been developed. Extremely-low-power adiabatic logic circuit scheme has also been developed for the gigascale integrated circuit.3. Limit to the gigascale integrationOpportunities for gigascale integration are governed by a hierarchy of physical limits whose five levels can be classified as : fundamental, material, device, circuit, and system. This distinctive methodology is extended by elucidating the impact on gigascale integration of random dopant atom placement in the channel region of a MOSFET.4. Optimization of the system configurationBased on a newly derived complete stochastic interconnect distribution, an optimal wiring network architecture is defined that minimizes chip area and power dissipation. Less