Computer-Aided-Design for Analog-Digital Mixed Large Scaled Integration Circuits

(1)模拟布局约束分为两类，一类是人为设计人员明确指定的约束，另一类是由电路设计规范隐含导出的约束。后者必须定义良好，并纳入设计数据库。(2)为了在各种布局约束下获得高性能的详细路由，提出了一种设备级全局路由算法。为了提高算法的效率和满足更大的布局问题，该算法还进行了改进，引入了新的布局评估、函数和分治技术。(3)讨论了多芯片模块（MCM）的多层路由问题。MCM技术通常用作高密度封装技术，但其路由问题类似于模拟路由问题，例如最小的线长，较少的路由层或较少的过孔，以及防止信号干扰或串扰噪声。我们改进了一种V4R算法，实验结果表明，我们的方法在路由总长度上是相当好的。讨论了获得最优路径的算法参数。(4)对商用CAD系统进行了研究，并尝试设计了一些样电路、一个微处理器和一个简单的应用电路。比较了HDL设计与常规门级设计的设计效率。我们还讨论了测试生成问题，并提出了一种有效的组合电路测试方法和一种冗余故障检测方法。

(1) Analog Layout Constraints were classified into two groups, constraints explicitly specified by human designers and constraints implicitly derived from circuit design specifications. The latter must be well-defined and incorporated in a design data-base.(2) A device-level global rouitng algorithm was proposed in order to obtain high-performance detailed routing under various layout constraints. The algorithm was also improved to increase efficiency and to meet with a larger layout problem, introducing a new layout-evaluation, function and a divide-and-conquer technique.(3) A multi-layrs rouitng problem was disscussed for Multi-Chip Modules (MCM). An MCM technology is usually used as higher-density packaging technology, but its routing ploblems are similar to analog routing problems such that minimum wire-length, less routing-layrs or less vias used, and preventing signal interference or cross-talk noise. We improved a V4R algorithm and experimental results show that our approach is fairly good in the total routing length. We also discussed algorithm parameters to obtain an optimum routes.(4) Commercial CAD systems were investigated and tried to design some sample circuit, a micro-proceesor and an simple application circuit. Design efficiency was compared between HDL design and conventional gate-level design. We also discussed test generation problems, and proposed an efficient testing for combinatorial circuits and a redundant fault detection for sequential circuits.