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High-Performance Parallel Simulation Technology for Advanced Information System Development

High-Performance Parallel Simulation Technology for Advanced Information System Development
先进信息系统开发的高性能并行仿真技术
批准号:
17300015
负责人:
NAKASHIMA Hiroshi
金额:
$9.63万
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (B)
财政年份:
2005
资助国家:
日本
项目状态:
已结题
起止时间:
2005 至 2007

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中文摘要
翻译
针对以微处理器为核心部件的先进IT系统的周期精确仿真(CAS)并行化和性能提升问题展开了研究。主要研究成果有以下几个方面:1.仿真技术。我们的并行化CAS与有序执行模拟器相结合,以产生并行模拟的近似部分结果。为了避免这种顺序顺序模拟器成为瓶颈,我们设计了一种加速技术来自动生成针对每个工作负载的模拟器。该技术可将指令级模拟的性能提高高达34倍。我们设计了一种新的并行模拟方法,将模拟过程沿时间轴划分为多个间隔,从而使多个间隔并行执行,从而解决了由于间隔间的依赖而引起的问题。该方法是用顺序模拟的方法推测地执行每个间隔,其结果近似于先前间隔的部分结果。因此,我们在8节点PC集群上的并行执行速度提高了5.8倍。为了估计实时系统设计中所需要的中断造成的最坏情况的延迟,我们设计了O(FN)算法来分析具有N条指令和F个中断的工作负载的缓存和分支预测器的最坏情况下的未命中增量。此外,我们设计了一种O(NlogN)算法来精确地计算延迟本身,该算法可以通过并行化来加速,在8节点的PC集群上最多可以加速9倍。
英文摘要
The research has been pursued aiming at the parallelization and performance improvement of cycle accurate simulation (CAS) for advanced IT systems with microprocessors as their key components. The major achievements of the research are the following simulation techniques.1. Our parallelized CAS is combined with an in-order execution simulator to produce approximated partial results of the parallel simulation. In order to avoid that this sequential in-order simulator became a bottleneck, we devised an acceleration technique to generate a simulator specific to each workload automatically. This technique achieves up to 34-fold performance improvement for instruction level simulation.2. We devised a new parallel simulation method in which the process of a simulation is divided into intervals along with time axis so that the intervals me executed in parallel The problem arisen from the dependency between intervals is solved by speculatively executing each interval with approximated partial result of preceding intervals using in-order simulation. As a result, our parallel execution with an eight-node PC cluster achieves up to 5.8-fold speed-up.3. To estimate the worst-case delay caused by interrupts, which is required in the design of real-time systems, we devised O (FN) algorithms to analyze the worst-case miss increments of caches and branch predictors for a workload with N instructions and F interrupts. Furthermore, we devised a O (Nlog N)algorithm to calculate the delay itself accurately using CAS, which can be accelerated by parallelization, up to 9-fold with an eight-node PC cluster.
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会议论文
少しは組込的なアーキテクチャシミュレーション---色々やってわかったこと---(招待講演)
一点点嵌入式架构模拟---我从做各种事情中学到的东西---(特邀演讲)
DOI: --
发表时间: 2007
期刊: 情報処理学会研究報告 2007-ARC-171
影响因子: --
作者: [古川貴士, 近田慎一郎, 本田晋也, 冨山宏之, 高田広章, 亀山充隆, 中島浩]
通讯作者: 中島浩
時間軸分割並列マイクロプロセッサシミュレータの高速化手法
时轴分离并行微处理器模拟器的加速方法
DOI: --
发表时间: 2006
期刊: 情報処理学会研究報告 2006-ARC-169
影响因子: --
作者: [矢野聖宗, 中田尚, 津邑公暁, 中島浩]
通讯作者: 中島浩
Design and Implementation of a Workload Optimized Simulator (in Japanese)
工作负载优化模拟器的设计与实现(日语)
DOI: --
发表时间: 2005
期刊: IPSJ Trans Advanced Computing Systems 46(SIG12)
影响因子: --
作者: [Takashi, Nakada, Tomoaki, Tsumura, Hiroshi, Nakashima]
通讯作者: Nakashima
DOI: --
发表时间: 2007
期刊: 情報処理学会研究報告 2007-ARC-172
影响因子: --
作者: [矢野聖宗, 高崎透, 中田尚, 中島浩]
通讯作者: 中島浩
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      25870694
    • 项目类别:
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    • 资助金额:
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    • 财政年份:
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    • 财政年份:
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    • 负责人:
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    • 批准号:
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    • 项目类别:
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    • 资助金额:
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    • 财政年份:
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