System Integration of Beyond-Binary Computing

目前的超大规模集成电路系统是基于二进制（基数-2）算法与二进制逻辑器件相结合而设计的。随着VLSI技术缩小到深亚微米几何结构，由布线复杂性和延迟增加引起的性能瓶颈变得非常严重。为了克服性能瓶颈，本研究项目研究了基于一种称为“超越二进制计算”的新型计算范式的系统集成。以下是本项目的主要成果：开发了一种硬件描述语言ARITH，用于描述VLSI系统中的硬件算法。通过使用ARUM，我们开发了一个先进的库，其中包含使用二进制和非二进制数字系统的高性能算术算法。作为应用，我们使用所提出的库开发了一个实用的模块生成器，支持各种乘法器结构。发电机可从我们的网站，并在世界各地广泛使用。…更多提出了一种利用ARITH设计高性能超二进制算术电路的高级设计方法。在二进制/多值融合逻辑中，ARITH描述可以转化为与技术相关的网表。对于原型设计，我们分别使用电压模式和电流模式CMOS技术实现二进制逻辑和多值逻辑。将网表转换为物理布局模式的过程由现成的放置和路由工具自动执行。通过一些算法电路的设计，验证了该方法的性能。为研究下一代低功耗大规模集成电路，提出了一种基于单电子晶体管（set）的内容可寻址存储电路。此外，实验研究了一种利用人工催化剂器件实现无线电路集成的氧化还原微阵列。通过可激发反应扩散动力学演示了氧化还原微阵列的原型。上反应)。对化学波的可视化进行了研究。少

The present-day VLSI systems are designed on the basis of binary (radix-2) arithmetic algorithms combined with binary logic devices. As the VLSI technology scales down to deep sub-micron geometry, performance bottlenecks caused by increased wiring complexity and delay are becoming significantly severe. In order to overcome the performance bottlenecks, this research project investigates system integration based on a novel computing paradigm called "Beyond-Binary Computing". Listed below are major results of this project :1. A hardware description language called ARITH was developed for describing hardware algorithms in VLSI systems. By using ARUM, we developed an advanced library containing high-performance arithmetic algorithms using both binary and non-binary number systems. As an application, we used the proposed library to develop a practical module generator supporting various multiplier structures. The generator is available from our website, and is widely used all over the world. … More 2. A new high-level design method with ARITH was developed for designing high-performance beyond-binary arithmetic circuits. The ARITH description can be transformed into a technology-dependent netlist in binary/multiple-valued fused logic. For the prototype design, we used voltage-mode and current-mode CMOS technologies for binary logic and multiple-valued logic, respectively. The process of transforming the netlist into a physical layout pattern is automatically performed by an off-the-shelf place-and-route tool. The capability of the proposed method was investigated through some arithmetic circuit designs.3. A content-addressable memory circuits based on Single-Electron Transistors (SETs) was developed and evaluated for studying next-generation low-power LSI circuits. Also, a redox microarray for wire-free circuit integration using artificial catalyst devices was investigated experimentally. A prototype of redox microarray was demonstrated through an excitable reaction-diffusion dynamics, which was implemented by chemical reaction(e.g. B-Z reaction)waves. The visualization of the chemical waves was also investigated. Less