ENIAC MOdeling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems (MODERN)

在45纳米技术时代，不断增加的CMOS器件变化性已成为半导体制造和设计行业面临的最尖锐的问题之一。在所有可能的可变性来源中，由电荷的离散性和物质的粒度引入的统计可变性是所有来源中最有问题的，这些晶体管已经具有分子尺寸的特征。与统计可变性相结合，负偏置温度不稳定性(NBTI)和/或热载流子退化可能导致严重的统计可靠性问题。人们普遍认为，技术计算机辅助设计(TCAD)和电子设计自动化(EDA)工具都缺乏必要的能力来预测和解决技术和电路设计过程中日益增长的可变性和可靠性问题。欧洲纳米技术平台ENIAC的战略研究议程(SRA)和ENIAC联合开展多年度战略计划强调了这一不足以及相应的工具开发需求。这一问题在2008年ENIAC第一次征求建议书和相应的2008年ENIAC年度工作方案中被列为优先事项。欧洲半导体和设计业、研究机构和选定的学术界研究团体对ENIAC的呼吁做出了迅速反应，组建了一个强大的财团来解决SP7的优先事项。格拉斯哥的DMG在统计可变性的模拟和预测方面处于世界领先地位，已被邀请作为相应的ENIAC现代提案的主要合作伙伴。这项提议是旨在支持DMG参与ENIAC现代的一揽子资金计划的一部分，其中包括来自ENIAC、EPSRC和苏格兰企业的资金。这将肯定英国在该领域的领先地位，但更重要的是，将向充满活力的英国CMOS器件和设计社区提供相关的知识、专业知识和模拟工具，并将为充满活力的英国设计行业带来竞争优势。它还将培训技术、器件和设计之间的接口方面的专家，这是英国的小企业和寓言设计公司，如ARM、CSR、沃森微电子和许多从事芯片设计活动的英国中小企业所急需的。

Increasing CMOS device variability has become one of the most acute problems facing the semiconductor manufacturing and design industries at, and beyond, the 45 nm technology generation. From all possible sources of variability the statistical variability introduced by the discreteness of charge and granularity of matter in transistors with features already of molecular dimensions is the most problematic of all. In conjunction with the statistical variability the negative bias temperature instability (NBTI) and/or hot carrier degradation can result in acute statistical reliability problems. It is widely recognized that both technology computer aided design (TCAD) and electronic design automation (EDA) tools lack the essential capabilities to predict and compass the increasing variability and reliability problems in the technology and circuit design process. This deficiency, and the corresponding tool development needs, were highlighted in the Strategic Research Agenda (SRA) of the European Nanotechnology Platform ENIAC and in the ENIAC Joint Undertaking Multi-Annual Strategic Plan. It was prioritized in the first 2008 ENIAC call for proposals and the corresponding 2008 ENIAC Annual Work Programme. The European semiconductor and design industry, research institutes and selected academia based research groups have reacted swiftly to the ENIAC call putting together a powerful consortium to address the SP7 priorities. The DMG at Glasgow, which is a world leader in the simulation and forecasting of statistical variability, has been invited as a key partner in the corresponding ENIAC MODERN proposal. This proposal is part of the funding package designed to support the DMG participation in ENIAC MODERN and includes funding from ENIAC, EPSRC and Scottish Enterprise. This will affirm the UK's leadership position in this field but more importantly will make available the associated knowledge, expertise and simulation tools to the vibrant UK CMOS device and design communities and will give a competitive advantage to the vibrant UK design industry. It will also train experts at the interface between technology, devices and design which are much needed in the UK chiples and fables design companies like ARM, CSR, Wofson Microelectronics and the numerous UK SMEs with chip design activities.