Tunnel epitaxy: building a buffer-less III-V-on-insulator (XOI) platform for on-chip light sources

在过去的几十年里，半导体材料和器件技术取得了爆炸性的增长，并对现代社会的塑造产生了深远的影响。在经历了90年代个人电脑(PC)技术的蓬勃发展和21世纪头10年互联网的热潮之后，我们正在拥抱物联网的新时代。随着互联网协议(IP)流量的爆炸性增长将数据中心推向所谓的“Zetabyte时代”，由于铜线的欧姆损耗和RC延迟，今天的电气互连迅速成为瓶颈。光学互连有望打破瓶颈，使计算机中的数据能够跨芯片移动，并通过光子在芯片之间移动。光子是频率很高的电磁波。它们可以以光速飞行，是超高效的信息载体。光学互连的实现需要将从无源器件到有源器件的所有光学元件集成在同一绝缘体上硅平台上。尽管在开发硅基光调制和检测方面取得了巨大成功，但由于硅的间接带隙特性而缺乏有效的光发射器仍然是一个主要的障碍。与硅相比，大多数III-V化合物半导体具有直接禁带，具有良好的光子吸收和发射效率。人们普遍认为，在硅上集成III-V半导体可以解锁从电互连到光学互连的过渡。在硅上的所需区域外延生长III-V材料提供了一种可扩展、低成本和高通量的方案，为硅集成电路带来光学功能。然而，与材料不兼容相关的几个基本挑战，包括晶格常数和热膨胀系数的大失配，以及极性材料在非极性衬底上的生长。传统的III-V/Si外延通过体硅晶片上的多个缓冲层绕过了这些挑战。然而，厚缓冲器限制了工艺吞吐量，并为有效地将光耦合到底层硅波导提供了一大障碍。在这个项目中，将开发一种先进的外延工艺，以实现在硅晶片上集成的III-V On绝缘体(XOI)结构。通过利用有限空间中的晶体地理和选择性区域生长，我们的目标是在绝缘体上实现无位错的微尺寸薄膜，而不需要复杂的缓冲器设计。这种无缓冲器的平台可能支持III-V化合物半导体与硅波导的紧密集成，并在硅光子学中打开巨大的机会。作为概念验证，将制造微盘激光器，以验证III-V结构的光学质量，并突出其在光子学集成方面的潜力。

The past few decades have witnessed an explosive growth in the semiconductor material and device technologies and their profound impact in the shaping of modern society. After experiencing the booming development of personal computer (PC) technology in the 1990s and the upsurge of the Internet in the 2000s, we are embracing a new age of the Internet of Things. As the explosive growth of Internet Protocol (IP) traffic is driving data centres to the so-called "Zettabyte Era", today's electrical interconnects quickly became the bottleneck due to ohmic loss and RC delays of copper wires. Optical interconnects promise to break the bottleneck by enabling data in computers moving both across chips and from chip to chip through photons. Photons are electromagnetic waves with very high frequencies. They can travel at the speed of light and they are super-efficient information carriers. The realisation of optical interconnects requires all optical components from passive to active devices to be integrated on the same silicon-on-insulator platform. Despite great success in developing silicon-based light modulation and detection, the lack of an efficient light emitter due to the indirect bandgap properties of silicon continues to pose a major roadblock. In contrast to silicon, most of III-V compound semiconductors have a direct bandgap with excellent photon absorption and emission efficiency. It is widely perceived that integrating III-V semiconductors, the best available materials for light emitters, on silicon could unpin the transition from electrical to optical interconnects.Epitaxial growth of III-V materials in the desired areas on silicon offers a scalable, low-cost and high-throughput scheme to bring optical capabilities to silicon integrated circuits. However, there are several fundamental challenges associated with material incompatibility, including a large mismatch in the lattice constants and thermal expansion coefficients, and the growth of polar materials on non-polar substrates. Conventional III-V/Si epitaxy circumvents these challenges through multiple buffer layers on bulk silicon wafers. However, thick buffers limit process throughput and present a big barrier for efficient light coupling to the underlying silicon waveguides. In this project, an advanced epitaxy process will be developed to enable an III-V on insulator (XOI) structure integrated on silicon wafers. By taking advantage of the crystallographic geography and selective area growth in confined spaces, we aim to achieve dislocation-free micro-sized thin films on insulators without requesting complex buffer designs. Such a buffer-less platform can potentially support intimate integration of III-V compound semiconductors with silicon waveguides and open enormous opportunities in Si photonics. As a proof-of-concept demonstration, micro-disk lasers will be fabricated to validate the optical quality of the III-V structures and highlight its potential for photonics integration.