Area and power efficient interconnect architecture for multi-bit processing on FPGAs

现场可编程门阵列（fpga）是设计用于实现数字系统的器件。它们针对硬件算法进行了优化，并且具有能够在几分之一秒内更改其功能的附加优势。作为面向硬件和可编程的，fpga提供了独特的性能和功能的混合，这对许多应用来说是必不可少的。fpga每年有超过80,000个设计启动和40亿美元的销售额，已经成为最受欢迎的计算媒体之一。fpga的可编程性使其设计特别具有挑战性。通常只有25%的FPGA面积用于执行计算。其余75%用于将计算元素连接在一起。因此，FPGA互连的设计与计算元件的设计一样重要。本研究的目标是增加FPGA互连的面积和功率效率。实际上，该领域的所有现有研究都涉及一次处理一位信息的计算元件。然而，现代的fpga也包含设计用于同时处理多比特信息的元件。这些多比特处理元素的使用越来越多，这给问题带来了新的未知方面和变量。在这项工作中，我们将重点关注多比特处理元件的两个独特属性——它们的信号的相关行为和它们的大小变化。首先，我们将利用相关行为来开发互连的转换能力，以提高面积和功率效率。然后，我们将研究将不同大小的计算单元连接在一起的最有效方法。最后，我们将研究如何将单比特处理元件分组成多比特处理单元，以提高其互连的效率。

Field-Programmable Gate Arrays (FPGAs) are devices that are designed to implement digital systems. They are optimized for hardware algorithms and have the added advantages of being able to change their functionalities in a fraction of a second. Being both hardware-oriented and programmable, FPGAs provide a unique blend of performance and functionality that is essential to many applications. With over 80,000 design-starts and $4 billion in sales annually, FPGAs have become one of the most popular computing media.     The programmability of FPGAs has made their design particularly challenging. Typically only 25% of FPGA area is used to perform computation. The remaining 75% is used to connect the computing elements together. Consequently, the design of FPGA interconnects can be as important as the design of the computing elements.     The goal of this research is to increase the area and power efficiency of FPGA interconnects. Virtually all existing investigations in the field have dealt with computing elements that process one bit of information at a time. Modern FPGAs, however, also contain elements that are designed to process multiple-bits of information simultaneously. The increased use of these multi-bit processing elements has introduced new unexplored aspects and variables to the problem.     In this work, we will focus on two unique properties of the multi-bit processing elements --- the correlated behaviours of their signals and their size variation. First, we will take advantage of the correlated behaviours to exploit the shift capabilities of interconnects for area and power efficiency. Then, we will investigate the most efficient method of connecting computing elements of various sizes together. Finally, we will study how the single-bit processing elements can be grouped into multi-bit processing units to improve the efficiency of their interconnects.