Digital and Memory Circuits in nano-scale CMOS Technologies

在现有技术中实现鲁棒集成电路正变得越来越困难。技术缩放使得晶体管容易受到工艺变化的影响，并且单个晶体管的不适当功能可能导致包含数百万个晶体管的芯片故障。通常，尽可能小的晶体管尺寸用于降低功率、能量消耗和增加封装密度。 不幸的是，具有较小尺寸的晶体管表现出对工艺变化的较高敏感性。特别地，低电压、低功率静态随机存取存储器（SRAM）电路由于最小可能的晶体管尺寸而显示出更高程度的变化。在本研究中，我们将探讨在电源和电压受限的环境下，数位SRAM电路的可变性感知设计。在微处理器中，高达70-80%的晶体管都在SRAM中。因此，片上系统（SoC）的各个方面-功率，能量，产量，质量和可靠性都受到SRAM的影响。 所提出的研究有两大部分-（a）SRAM电路，和（B）逻辑电路。在第一部分中，将研究SRAM的几个方面。本研究的主要目标是：（i）通过架构和电路创新降低SRAM功耗。我们将设计在亚阈值电压下工作的功能SRAM。(ii)设计电路技术，以减轻工艺变化对重要SRAM块（如读出放大器）的影响。我们将探讨新的架构和电路的灵敏放大器。(iii)设计软错误鲁棒的SRAM单元，可以从单粒子翻转中恢复。在第二部分的研究中，我们将研究高速数字电路工作在标称电压。对高速电路的研究必然涉及对高速逻辑类型的研究。这项工作建立在我们最近的研究恒定延迟（CD）逻辑风格。诸如加法器之类的构建模块将被设计为展示新逻辑家族在高速应用中的有效性。

Realization of robust integrated circuits in state of the art technologies is becoming increasingly difficult. The technology scaling makes transistors susceptible to process variations, and improper functioning of a single transistor may lead to the chip failure containing several million transistors. Often small as possible transistor sizes are used to reduce power, energy consumption, and to increase the packing density. Unfortunately, transistors with smaller dimensions exhibit a higher susceptibility to process variation. In particular, low-voltage, low-power Static Random Access Memory (SRAM) circuits show higher degree of variation owing to smallest possible transistor dimensions. In this research, we will investigate variability-aware design of digital, SRAM circuits in power and voltage constrained environments. In microprocessors up to 70-80% of transistors are in SRAMs. As a consequence, various aspects of Systems on Chip (SoC) - power, energy, yield, quality, and reliability are influenced by SRAMs. The proposed research has two broad segments - (a) SRAM circuits, and (b) logic circuits. In the first segment, few aspects of SRAMs will be investigated. The key objectives of this research are (i) to lower SRAM power consumption through architectural and circuit innovation. We will design functional SRAMs working at sub-threshold voltages. (ii) To devise circuit techniques to alleviate the impact of process variations on important SRAM blocks such as the sense amplifier. We will investigate new architectures and circuits for the sense amplifier. (iii) Design soft error robust SRAM cells that can recover from single event upsets. In the second segment of the research, we will investigate high speed digital circuits working at the nominal voltage. Research on high speed circuits will entail investigation of high speed logic styles. This work builds on our recent research on Constant Delay (CD) logic style. Building blocks such as adder will be designed to demonstrate effectiveness of new logic families for high-speed applications.