FSM Decomposition for Area and Performance Optimization: From Function to Layout

本研究的目标是开发一套集成的工具，用于减少面积和提高性能的顺序电路的逻辑和物理设计。所提议的研究是开发通过功能和物理分解来合成顺序电路的分析技术，以便最小化面积和最大化性能（或在两者之间找到折衷）。将一个顺序电路分解成一组相互作用的同步有限状态机（FSM）的算法正在被研究。该方法是找到一组机器状态的广义分区，使每个机器状态可以作为一个单独的机器来实现。与那些分区相对应的机器以一种比基于经典封闭分区理论的机器更复杂的方式相互作用。例如，在这种组织中，一台机器可能通过使用其他机器的状态位作为主要输入来依赖其他机器。

The goal of this research is the development of an integrated set of tools for the logical and physical design of sequential circuits with reduced area and improved performance. The proposed research is developing analytical techniques for synthesis of sequential circuits by means of functional and physical decompositions so as to minimize the area and maximize the performance (or find a trade off between the two). Algorithms to decompose a sequential circuit into a set of interacting synchronous finite state machines (FSM's) are being investigated. The approach is to find a set of generalized partitions of machine states, so that each machine state can be implemented as a separate machine. The machines corresponding to those partitions interact with each other in a more complex fashion than those derived on the basis of classical theory of closed partitions. For example, in this organization one machine may depend on other machines by using their state bits as primary inputs.