High-Performance VLSI Synthesis with Wave Pipelining

Ciesielski波流水线是一种高性能的电路设计方法，它在逻辑上实现流水线，而不需要使用中间锁存器。因此，与不同时钟周期相关的几个计算波(信号)可以同时通过该逻辑传播。这项研究扩展了以往静态逻辑中的波形流水线的实现，包括了以面积更小、性能更高而闻名的动态CMOS逻辑。以前的波流水线工作使用在信号线和时钟线上插入延迟元件来均衡路径延迟。这些延迟通常是不精确的，可能需要大量的VLSI面积。为了避免这些问题，我们通过在逻辑块内重组计算来均衡路径。使用现代逻辑综合工具的逻辑级别的重组是针对高度结构化的计算和规则数组的。这些新方法已在一套CAD工具中实现，以使VLSI自动综合系统中的波形流水线可用。几个VLSI测试芯片正在设计、制造和测试中，以验证我们的方法和CAD工具的可行性。

Ciesielski Wave-pipelining is a method of high-performance circuit design which implements pipelining in logic without the use of intermediate latches. As a result, several computation waves (signals) related to different clock cycles can propagate through the logic simultaneously. This research extends previous implementations of wave-pipelining in static logic to include dynamic CMOS logic which is known for its smaller area and higher-performance. Previous work in wave-pipelining uses the insertion of delay elements on signal and clock lines to equalize path delays. These delays are often imprecise and can require a significant amount of VLSI area. To avoid these problems, we equalize the paths by restructuring the computation within the logic block. The restructuring at the logic level, using tools of modern logic synthesis, is targeted towards highly structured computations and regular arrays. The new methods are implemented in a suite of CAD tools to make wave pipelining accessible in automatic VLSI synthesis systems. Several VLSI test chips are being designed, fabricated and tested to verify the feasibility of our methods and CAD tools.