Gate Dielectric for Scaled CMOS Technology

点击翻译按钮获取中文摘要

9817869MaThis proposed research will focus on the synthesis, characterization, and application of the Jet-Vapor-Deposited (JVD) silicon nitride (abbreviated SiN) and titanium oxide (designated TiO2) as advanced gate dielectrics for future generations of CMOS technology.It is widely believed that the thermal Si02 will no longer be acceptable as the gate dielectric for many applications when its thickness shrinks to around 2 nm or below, due to the excessive leakage current arising from direct tunneling. According to "The National Technology Roadmap for Semiconductors" (NTRS), published by the Semiconductor Industry Association in 1997, such an oxide thickness is required for main stream products to be introduced in the year 2006, less than a decade away.Of the numerous possible alternative gate dielectrics that we have investigated, either through literature search or through in-house research, none has been found to be as promising as the JVD SiN. Our study so far indicates that many of the key electronic properties of the JVD SiN, deposited directly on Si at room temperature, are comparable to or better than thermal SiO2, especially in the ultra-thin regime. These include the high breakdown strength, the low trap density, the low dielectric charge density, the low gate leakage current, the low stress-induced leakage current, and the high resistance to boron penetration, of which the latter three are far better than thermal SiO2. The higher dielectric constant of the JVD SiN (nearly twice that of the thermal SiO2) allows a thicker gate dielectric to be used to achieve the same gate capacity, which should translate into better controllability and manufacturability. It is estimated that the JVD SiN may satisfy the gate dielectric requirement upto year 2006, or 1.5-2 nm thickness range, according to the NTRS.Beyond year 2005, a higher her dielectric constant is needed. We propose to target JVD TiO2 in this study, as our preliminary results in the EOT range of around 2 nm look very promising. While others have tried Ti02 as a potential gate dielectric on Si, these films are all thicker than 4 nm of EOT (equivalent oxide thickness), partly clue tothe inevitable growth of a substantial SiO2 layer between Si and the TiO2 film during TiO2 deposition and subsequent processes. In our case, we used ultra-thin JVD SiN ( 1 nm) as a buffer between the Si substrate and the deposited TiO2 film, which prevented oxidation of the Si substrate. We believe that this approach will allow the gate dielectric scaling to continue beyond year 2009, or below 1.5 nm of EOT.JVD is a novel process for synthesizing a wide variety of thin films of metals, semiconductors, and insulators. It relies on supersonic jets of a light carrier gas such as helium to transport depositing vapor from the source to the substrate. Because of the separation of the constituent depositing species, and the short transit time, there is very little chance for gas-phase nucleation. We believe the high impact energies of the depositing species also contribute to the improved film quality.This research project will address a number of important scientific as well as technological issues related to the JVD SiN and JVD Ti02 in the sub-2-nm EOT range. The potential impact of this research is very significant, as it not only promises to advance our knowledge on two very promising electronic materials, but also leads to a better understanding of the JVD method as a generic tech-nology for synthesizing a variety of thin and thick films. The potential impact of this research on the nation's economy, should it be successfully implemented by the semiconductor inductory, could be tremendous, as it will enable continued scaling of CMOS technology several generations beyond what is possible with the conventional thermal SiO2.***