Gate Dielectric for Scaled CMOS Technology

用于缩放 CMOS 技术的栅极电介质

• 批准号: 9817869
• 负责人: Tso-Ping Ma
• 金额: $ 18万
• 依托单位: Yale University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1999
• 资助国家: 美国
• 起止时间: 1999-05-01 至 2002-04-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9817869&HistoricalAwards=false
• 关键词: Gate; Dielectric; Scaled; CMOS; Technology

9817869MaThis proposed research will focus on the synthesis, characterization, and application of the Jet-Vapor-Deposited (JVD) silicon nitride (abbreviated SiN) and titanium oxide (designated TiO2) as advanced gate dielectrics for future generations of CMOS technology.It is widely believed that the thermal Si02 will no longer be acceptable as the gate dielectric for many applications when its thickness shrinks to around 2 nm or below, due to the excessive leakage current arising from direct tunneling. According to "The National Technology Roadmap for Semiconductors" (NTRS), published by the Semiconductor Industry Association in 1997, such an oxide thickness is required for main stream products to be introduced in the year 2006, less than a decade away.Of the numerous possible alternative gate dielectrics that we have investigated, either through literature search or through in-house research, none has been found to be as promising as the JVD SiN. Our study so far indicates that many of the key electronic properties of the JVD SiN, deposited directly on Si at room temperature, are comparable to or better than thermal SiO2, especially in the ultra-thin regime. These include the high breakdown strength, the low trap density, the low dielectric charge density, the low gate leakage current, the low stress-induced leakage current, and the high resistance to boron penetration, of which the latter three are far better than thermal SiO2. The higher dielectric constant of the JVD SiN (nearly twice that of the thermal SiO2) allows a thicker gate dielectric to be used to achieve the same gate capacity, which should translate into better controllability and manufacturability. It is estimated that the JVD SiN may satisfy the gate dielectric requirement upto year 2006, or 1.5-2 nm thickness range, according to the NTRS.Beyond year 2005, a higher her dielectric constant is needed. We propose to target JVD TiO2 in this study, as our preliminary results in the EOT range of around 2 nm look very promising. While others have tried Ti02 as a potential gate dielectric on Si, these films are all thicker than 4 nm of EOT (equivalent oxide thickness), partly clue tothe inevitable growth of a substantial SiO2 layer between Si and the TiO2 film during TiO2 deposition and subsequent processes. In our case, we used ultra-thin JVD SiN ( 1 nm) as a buffer between the Si substrate and the deposited TiO2 film, which prevented oxidation of the Si substrate. We believe that this approach will allow the gate dielectric scaling to continue beyond year 2009, or below 1.5 nm of EOT.JVD is a novel process for synthesizing a wide variety of thin films of metals, semiconductors, and insulators. It relies on supersonic jets of a light carrier gas such as helium to transport depositing vapor from the source to the substrate. Because of the separation of the constituent depositing species, and the short transit time, there is very little chance for gas-phase nucleation. We believe the high impact energies of the depositing species also contribute to the improved film quality.This research project will address a number of important scientific as well as technological issues related to the JVD SiN and JVD Ti02 in the sub-2-nm EOT range. The potential impact of this research is very significant, as it not only promises to advance our knowledge on two very promising electronic materials, but also leads to a better understanding of the JVD method as a generic tech-nology for synthesizing a variety of thin and thick films. The potential impact of this research on the nation's economy, should it be successfully implemented by the semiconductor inductory, could be tremendous, as it will enable continued scaling of CMOS technology several generations beyond what is possible with the conventional thermal SiO2.***

9817869 Ma本研究将集中在合成，表征，喷射气相沉积（JVD）氮化硅及其应用（缩写为SiN）和氧化钛（指定为TiO 2）广泛认为，当热SiO2的厚度收缩到约2nm时，热SiO2将不再被接受作为用于许多应用的栅极电介质或更低，这是由于直接隧穿引起的过量漏电流。根据1997年由半导体工业协会出版的“半导体国家技术路线图”（NTRS），这样的氧化物厚度是2006年（不到10年）推出的主流产品所需要的。在我们通过文献搜索或通过内部研究调查的众多可能的替代栅极晶体管中，但是还没有发现像JVD SiN那样有希望。到目前为止，我们的研究表明，在室温下直接沉积在Si上的JVD SiN的许多关键电子性质与热SiO2相当或更好，特别是在超薄范围内。这些特性包括高击穿强度、低陷阱密度、低介质电荷密度、低栅漏电流、低应力诱导漏电流和高抗硼渗透性，其中后三者远远优于热SiO2。JVD SiN的较高介电常数（几乎是热SiO2的两倍）允许使用较厚的栅极电介质来实现相同的栅极容量，这应该转化为更好的可控性和可制造性。根据NTRS，预计到2006年，JVD SiN可以满足1.5- 2nm厚度的栅介质要求，而到2005年以后，则需要更高的介电常数。我们建议在这项研究中以JVD TiO 2为目标，因为我们在约2 nm的EOT范围内的初步结果看起来非常有希望。虽然其他人已经尝试将TiO 2作为Si上的潜在栅极电介质，但这些膜都厚于4 nm的EOT（等效氧化物厚度），部分原因在于在TiO 2沉积和后续工艺期间，在Si和TiO 2膜之间不可避免地生长大量SiO2层。在我们的情况下，我们使用超薄JVD SiN（1 nm）作为Si衬底和沉积的TiO 2膜之间的缓冲层，防止Si衬底氧化。我们相信，这种方法将使栅极电介质缩放继续超过2009年，或低于1.5 nm的EOT。JVD是一种新颖的工艺，用于合成各种各样的金属，半导体和绝缘体薄膜。它依赖于轻载气（如氦气）的超音速射流将沉积蒸汽从源输送到衬底。由于组分沉积物质的分离和短的渡越时间，气相成核的机会非常小。我们相信沉积物质的高冲击能量也有助于提高薄膜质量。这项研究项目将解决与JVD SiN和JVD TiO 2在亚2 nm EOT范围内相关的许多重要科学和技术问题。这项研究的潜在影响是非常重要的，因为它不仅有望提高我们对两种非常有前途的电子材料的认识，而且还可以更好地理解JVD方法作为合成各种薄膜和厚膜的通用技术。这项研究对国家经济的潜在影响，如果它被成功地实施的半导体感应，可能是巨大的，因为它将使CMOS技术的持续规模超过几代传统的热SiO2。