NSF/ENG/ECCS-BSF: Dynamically configurable memory technology based on ferroelectric-gated field effect transistors

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The main objective of this NSF/ENG/ECCS-BSF proposal is to demonstrate the feasibility and scalability of a novel dynamically configurable memory technology based on ferroelectric-gated FET's (FeFET's). Specifically, the 'dynamical configurability' enables the fabricated memory array to behave as either nonvolatile memory (NVM, with 10 years retention time and 105-106 endurance cycles) or as DRAM (with 1012 endurance cycles but 1 hour retention) by adjusting the write/erase programming strength. This unprecedented capability is a paradigm shift from the conventional semiconductor memory in which the NVM and DRAM are two entirely different technologies and have rigid boundaries to separate them. The successful breakthrough of these rigid boundaries through proposed research project will open up numerous opportunities for device engineers, circuit designers, and systems integrators to continue to push the frontiers of the conventional scaling approach of both NVM and DRAM technologies. The PI and Co-PI outreach activities involves recruitment of undergraduates and K-8 teachers from neighboring Southern Connecticut State University which has 25+% underrepresented minority enrollment and trains K-8 teachers, for participation in the proposed research project. The proposed dynamically configurable memory technology represents a paradigm shift from the conventional concept of pitting nonvolatile memory (NVM) against DRAM, where the two memory technologies are considered to be fundamentally different, not only in the basic memory cell structure but also in the array architecture, and operating principles. To achieve this objective, the PI/Co-PI at Yale University in collaboration with the research team at the Technion-Israel Institute of Technology will take advantage of complementary strengths in addressing fundamental as well as technological issues related to device physics, device engineering, device fabrication, modeling/simulation, circuit design, device/circuit characterization, and materials science, to achieve the research objective. The successful demonstration of this proposed research will serve to break through all these boundaries, as the same fabricated hardware will serve the functionality of both NVM and DRAM in a system by merely controlling the programming software. For the semiconductor memory community, this will open up new opportunities for innovative research that goes beyond the conventional methodology that is confined by the traditional boundaries between the compartmentalized NVM and DRAM.