Inelastic Electron Tunneling Spectroscopy Studies of Advanced Gate Dielectrics

先进栅极电介质的非弹性电子隧道光谱研究

• 批准号: 0096762
• 负责人: Tso-Ping Ma
• 金额: $ 35.15万
• 依托单位: Yale University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2001
• 资助国家: 美国
• 起止时间: 2001-03-15 至 2004-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0096762&HistoricalAwards=false
• 关键词: Inelastic; Electron; Tunneling; Spectroscopy; Studies

This project has two related thrusts; the application of Inelastic Electron Tunneling Spectroscopy(IETS) to achieve greater understanding and improvement of gate oxides, and the materials science of jet vapor deposited(JVD) dielectrics. With gate oxides only a few monolayers thick, it becomes increasingly difficult for conventional dielectric characterization tools, such as infrared spectroscopy and Raman spectroscopy to reveal structural and compositional information accurately. In addition, large gate leakage currents also make a number of widely used electrical measurements, such as C-V, G-V, and charge-pumping, either extremely difficult or impossible to implement. IETS relies on tunneling current to probe the ultra-thin gate dielectric in a metal-insulator-semiconductor (MIS) sandwich and becomes more sensitive when the tunneling current increases. Examples of information from IETS include phonon modes of the gate electrode, phonon modes of the substrate, various vibrational modes of the gate dielectric, bonding structures and impurities in the gate dielectric, and traps as well as other electronic defects; all can be obtained on a sample volume of less than 10 -9 cc. Better understanding of the interactions between the tunneling electrons and the gate dielectric is expected. Information obtained from IETS will be correlated with characteristics of CMOS devices made with the same gate dielectrics, with a goal toward the optimization of high-k gate dielectrics.%%% The project addresses basic research issues in a topical area of materials science with high technological relevance. These studies will improve the fundamental understanding of gate dielectrics, which are key to advanced silicon-based microelectronics. An important feature of the program is the integration of research and education through the training of students in a fundamentally and technologically significant area. ***

该项目有两个相关的推动力；应用非弹性电子隧道谱(IETS)来实现对栅氧化物的更多了解和改进，以及喷射气相沉积(JVD)电介质的材料科学。由于栅氧化层只有几个单分子层厚，传统的介电表征工具，如红外光谱和拉曼光谱，越来越难以准确地揭示结构和成分信息。此外，大的栅漏电流也使得一些广泛使用的电测量，如C-V、G-V和电荷泵浦，要么极其困难，要么不可能实现。IETS依靠隧道电流探测金属-绝缘体-半导体(MIS)夹层中的超薄栅电介质，并且随着隧道电流的增加而变得更加灵敏。来自IETS的信息包括栅电极的声子模式、衬底的声子模式、栅电介质的各种振动模式、栅电介质中的成键结构和杂质、陷阱以及其他电子缺陷；所有这些都可以在小于10-9cc的样本体积上获得。人们希望更好地理解隧道电子和栅电介质之间的相互作用。从IETS获得的信息将与使用相同栅电介质制造的CMOS器件的特性相关联，目标是优化高k栅电介质。%该项目解决具有高度技术相关性的材料科学主题领域的基础研究问题。这些研究将提高对栅电介质的基本理解，这是先进的硅基微电子技术的关键。该计划的一个重要特点是通过在一个具有根本意义和技术意义的领域对学生进行培训，将研究和教育结合起来。***