Carrier Transport in Advanced Silicon Carbide (SiC) Devices

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0207093WhiteThis research program addresses the study of carrier transport in advanced silicon carbide (SiC) devices. The research focuses on the modeling, fabrication and electrical characterization of advanced SiC devices, including n and p-channel MOSFETs, and novel surface and buried-channel DIMOS and IGBT devices with particular emphasis on their utilization for power switching applications. The research emphasizes the development of a low temperature fabrication sequence to reduce the detrimental effects of 'step bunching', while simultaneously achieving the required activation of the implanted species. A goal of the research is to increase carrier inversion and accumulation-layer mobility through a combination of low temperature processing with an optimized gate dielectric. The research focuses on the physical modeling of carrier mobility where electrons move in localized states at the SiC-SiO2 interface and are thermally activated into extended states in the conduction band. A combination of thermal activation, surface roughness and point Coulomb scattering all play a role in limiting the carrier mobility and hence the specific ON resistance of SiC power MOSFETs. The study of both electron and hole transport is important in planar SiC integrated circuit technology, particularly for 'smart' power applications. The research employs novel test structures, fabrication techniques and instrumentation to study the influence of surface and bulk traps on carrier transport in inversion and layers over an extended temperature range, while contributing to the advancement of SiC devices, particularly power semiconductor devices.