Carrier Transport in Scaled Charge-Trap NVSM and CMOS Devices

摘要电荷陷阱非易失性半导体存储器和CMOS器件中的载流子输运本研究计划的目的是研究电荷陷阱非易失性半导体存储器和CMOS器件。我们的研究将集中在两个异质绝缘体器件结构：（1）金属和多晶硅栅极，高K，纳米级CMOS晶体管与固定电荷的高K电介质和（2）非易失性，电荷陷阱，纳米级SINOS半导体存储器件与可编程电荷存储。特别是，我们将专注于量子力学建模和实验表征的载流子迁移率退化，由于远程库仑和表面粗糙度散射，电荷传输和捕获和栅极泄漏在高K CMOS器件。电荷陷阱NVSM器件是具有栅极电介质的类SINOS结构，该栅极电介质包括隧道氧化物（O）、存储氮化硅（N）和作为氧化铝和/或二氧化铪的上覆高K阻挡氧化物（I），以增加膜的介电常数。我们将制作和模拟实验规模的5V SINOS器件，重点是写/写，保留和耐久性，并研究在氮化物中的载流子迁移率的存储电荷的影响。我们开发了一种新的技术，以提取低场载流子迁移率与两端C-V和G-V测量，允许异质绝缘栅介质的优化。SINOS器件提供了一个独特的机会，在Si-SiO2界面附近放置电荷，并探索它们对载流子迁移率的影响。我们将研究这些器件中的1/f和RTS噪声，重点是通过考虑捕获和自由电荷波动来统一现有理论。我们将补充与薄膜厚度和成分的材料测量的电气特性，特别是在使用原子层沉积（ALD）。此外，我们将采用高分辨率透射电子显微镜（HRTEM）和角分辨X射线光谱（ARXP）来研究薄膜厚度和结构特性及其与理论模型的关系。智力价值依赖于研究和教育的整合，以探索电荷陷阱NVSM和高K纳米级CMOS器件中的低场载流子输运，并对迁移率退化进行量子力学处理，电荷捕获、栅极泄漏、低频RTS和1/f噪声。我们检查迁移率与一个简单的两端电导/电容测量，以尽量减少需要制造完整的三端器件的欧姆接触，直到一个优化的栅极堆叠已在实验中确定。NVSM器件提供了一种独特的方法，可以在Si-SiO2界面附近电学定位和定位电荷中心，以研究它们对载流子传输和存储以及栅极泄漏和低频噪声的影响。我们的理论和实验研究将补充材料参数的变化，并使用先进的材料表征技术与HRTEM和ARXPS模拟纳米级NVSM和CMOS器件。在我们的计划更广泛的方面将推进纳米电子劳动力的多样性，并提供知识技术转让，研究和教育的整合，并促进与经济的工业部门的伙伴关系。我们已经制定了优秀的教育和推广计划，以增加在纳米电子学，特别是硅半导体器件的机会的多样性，一个重要的领域，以保持美国的领导地位，并为毕业生提供就业机会，在全球硅基半导体行业。我们的研究为少数民族学生的外展，实习和与行业的合作伙伴关系提供了一个很好的工具。 我们研究的变革性质在于（1）获得低电压、低功耗的NVSM的新方法，其具有交替的高K膜以保持势垒高度同时增加介电常数，（2）新的量子力学1/f噪声模型，以及（3）用简单的两端C-V和G-V结构模拟低场输运的新方法，其容易制造而不需要大量的焊接设备。该概念适用于研究新兴纳米器件（不一定是硅）中的载流子输运，并将有助于半导体技术领域的快速创新发展。

AbstractCarrier Transport in Scaled Charge-Trap NVSM and CMOS DevicesThe objective of the proposed research program is to study scaled charge-trap nonvolatile semiconductor memory (NVSM) and CMOS devices. Our study will focus on two hetero-insulator device structures: (1) metal and polysilicon gate, high-K, nanoscaled CMOS transistors with fixed charge in the high-K dielectric and (2) a nonvolatile, charge-trap, nanoscaled SINOS semiconductor memory device with programmable charge storage. In particular, we will focus on the quantum mechanical modeling and experimental characterization of carrier mobility degradation due to remote Coulomb and surface roughness scattering, charge transport and trapping and gate leakage in high-K CMOS devices. The charge trap NVSM devices are SINOSlike structures with a gate dielectric comprised of a tunnel oxide (O), a storage silicon nitride (N), and an overlying high-K blocking oxide (I) as aluminum oxide and/or hafnium dioxide to increase the dielectric constant of the film. We will fabricate and model experimental scaled 5V SINOS devices with an emphasis on Write/Erase, Retention and Endurance and study the influence of stored charge in the nitride on the carrier mobility. We have developed a novel technique to extract the low-field carrier mobility with a two-terminal C-V and G-V measurement to permit the optimization of the hetero-insulator gate dielectric. The SINOS devices offer a unique opportunity to electrically place charge near the Si-SiO2 interface and to explore their influence on carrier mobility. We will examine 1/f and RTS noise in these devices with a focus on unifying existing theories through a consideration of both trapped and free charge fluctuations. We will complement the electrical characterization with material measurements on film thicknesses and compositions, especially in the use of atomic layer deposition (ALD). In addition, we will employ high-resolution transmission electron microcopy (HRTEM) and angle-resolved X-ray photo spectroscopy (ARXP) to study film thickness and structural properties and their relation to theoretical models.The intellectual merit relies on an integration of research and education to explore low-field, carrier transport in charge-trap NVSM and high-K nanoscaled CMOS devices with a quantum mechanical treatment of mobility degradation, charge trapping, gate leakage, and low-frequency RTS and 1/f noise. We examine mobility with a simple two-terminal conductance/capacitance measurement to minimize the need to fabricate complete three-terminal devices with ohmic contacts until an optimized gate stack has been determined in the experiments. NVSM devices offer a unique approach to electrically locate and position charge centers in the vicinity of the Si-SiO2 interface to study their influence on carrier transport and storage as well as gate leakage and low-frequency noise. Our theoretical and experimental studies will be complemented with a variation of material parameters and the use of advanced materials characterization techniques with HRTEM and ARXPS to model nanoscaled NVSM and CMOS devices. The broader aspects in our program will advance diversity in the nanoelectronics workforce and provide intellectual technology transfer, integration of research and education, and promotion of partnerships with the industrial sector of the economy. We have developed excellent educational and outreach programs to increase diversity with opportunities in nanoelectronics, especially silicon semiconductor devices an important area to maintain US leadership and provide jobs for graduates in a global silicon-based semiconductor industry. Our research offers an excellent vehicle for minority student outreach, internships, and partnerships with industry. The transformative nature of our research lies in (1) a new approach to obtain low voltage, low power dissipation NVSMs with alternate high-K films to maintain barrier height while increasing the dielectric constant, (2) a new, quantum mechanical 1/f noise model, and (3) a novel method to model low field transport with simple two-terminal C-V and G-V structures, which is easily fabricated without extensive photolithographic equipment. The concept is applicable to the study of carrier transport in a broad range of emerging nanoscaled devices, not necessarily silicon, and will aid rapid and innovative advances in the field of semiconductor technology.