SHF:Small: Collaborative Research: Exploring 3-Dimensional Integration Strategies of STTRAM

高密度存储器的发展受到几个关键领域的最新进展的推动，这些领域包括大数据分析，物联网（IoT），可穿戴电子产品，智能手机，辅助设备，网络安全和天气跟踪系统。由于增加的能量消耗、可扩展性限制和有限的带宽，当前可用的常规存储器技术在解决这些需求方面面临严重的挑战。本提案的目的是通过使自旋扭矩转移RAM器件（STTRAM）与适当的选择二极管（SD）的3D集成来开发新型存储器件。这些类型的存储器设备将具有大规模可扩展性、节能性和快速性，这将为将它们集成到现有存储器架构中提供巨大的机会，以实现各种未来应用。该项目将通过将研究成果纳入PI的学术课程来整合教育。将通过合作寻求行业反馈。代表性不足的群体将通过宾夕法尼亚州立大学（PSU）和辛辛那提（UC）的几个外展项目参与科学和工程，如PSU的夏季研究机会项目（SROP），加州大学的新兴民族工程师（E3）计划，为来自市中心学校的高中生提供参加实习和实验室的机会，体验活动。本科生将通过两所大学的本科生研究经验（REU）计划参与研究。成果的传播将通过在高影响力的科学期刊上发表文章、会议演讲和YouTube讲座视频来完成。该项目的智力价值在于了解STTRAM器件与SD的集成兼容性，并基于集成STTRAM和SD开发高度可扩展的3D交叉阵列存储器技术。将通过执行以下具体目标来实现这些目标：（i）STTRAM-SD阵列的建模和仿真，（ii）弹性分析和优化研究，以最大限度地减少设备级可变性对性能指标的影响，（iii）STTRAM-SD架构的优化，以实现高性能计算和物联网，（iv）设计，制造，测试，以及基于能带设计和掺杂设计的过渡金属氧化物和电极叠层的新型SD器件的建模，（v）小尺寸STTRAM-SD阵列的设计和制造，电测试和建模以基准模拟和实验结果。预计该项目的成功完成将导致对STTRAM与SD的兼容性的基本理解，并提供开发高密度存储器的平台技术，这将对商业化和推进未来应用产生变革性影响。

The development of high-density memory is fueled by recent advancements in several critical areas ranging from big data analytics, Internet-of-Things (IoT), wearable electronics, smart phones, assistive devices, cybersecurity to weather tracking systems. Currently available conventional memory technologies face serious challenges in addressing these needs due to increased energy consumption, scalability limitations, and limited bandwidth. The objective of this proposal is to develop novel memory devices by enabling 3D integration of spin-torque transfer RAM devices (STTRAM) with appropriate selector diodes (SD). These types of memory devices will be massively scalable, energy-efficient, and fast which will open tremendous opportunities to integrate them in existing memory architectures to enable various futuristic applications. The project will integrate education by incorporating research outcomes in PI's academic courses. Industrial feedback will be sought via collaborations. Under-represented groups will be involved in science and engineering through several outreach programs at Penn State University (PSU) and University of Cincinnati (UC) such as Summer Research Opportunities Program (SROP) at PSU, and Emerging Ethnic Engineers (E3) program at UC which provides opportunities to the high-school students from the inner-city schools with economically challenged background to participate in internships and lab-experience activities. Undergraduate students will be involved in research via Research Experiences for Undergraduates (REU) program at both the universities. Dissemination of results will be accomplished by publications in high-impact scientific journals, conference presentations, and YouTube lecture videos. The intellectual merit of the project is in understanding the integration compatibility of STTRAM devices with SD and developing highly scalable 3D crossbar arrays of memory technologies based on integrated STTRAM and SD. The objectives will be achieved by executing the following specific aims: (i) modeling and simulation of STTRAM-SD arrays, (ii) resilience analysis and optimization studies to minimize the impact of device-level variabilities on performance metrics, (iii) optimization of STTRAM-SD architectures for high-performance computing and IoT, (iv) designing, fabrication, testing, and modeling of novel SD devices based on energy band-engineered and doping-engineered transition metal oxide and electrode stacks, (v) designing and fabrication of small-size STTRAM-SD arrays, electrical testing and modeling to benchmark simulations and experimental results. It is anticipated that the successful completion of this project will lead to a fundamental understanding of the compatibility of STTRAM with SD and provide a platform-technology to develop high-density memories which will have transformative impact on commercializing and advancing the futuristic applications.