Workshop on Devices-to-Systems for In-Memory Computing, being held Virtual at the University of Cincinnati, Cincinnati, Ohio, May 11-12, 2021.

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In-memory computing architectures are envisioned to be enablers for implementing data-driven algorithms using Machine Learning and Artificial Intelligence for applications, such as environment monitoring, healthcare, internet of things, mobile devices, communications, drones, and robots having tremendous societal impacts. Currently, a major question lies in understanding relative trade-offs between various available devices, identifying the most promising semiconductor device options, and research directions for developing novel devices for optimum functionality in-memory computing. This NSF workshop is being organized to explore novel devices and processes, enabling circuits and systems, integration and manufacturing, and semiconductor workforce development to establish US long-term leadership. The significance of this workshop includes identifying future nanoscale devices that will offer high-performance, low-cost, engineered and scalable functionality for performing in-memory computing operations at ultra-low power. The workshop will feature a dedicated session and panel discussions on education and workforce development that will include identification of challenges in semiconductor workforce development and future needs, interdisciplinary curriculum development in Electrical Engineering and Computer Science, efficient use of opensource platforms for in-memory devices and supporting technologies, equipment needs, and training of future scientists in these areas. The findings from this workshop will be summarized in a report and posted on workshop website for dissemination to the public at large. Additionally, the findings will be published as a peer-reviewed paper in an open access journal for broader dissemination to the scientific community. The technical significance of this workshop is to provide a platform for discussions on identifying the next generation of nanoscale devices to enable in-memory computing. The overall objective is to explore and identify the scientific issues and technological challenges associated with the underpinnings of in-memory computing. The workshop will invite leading researchers to discuss challenges associated with the currently available devices such as Static Random Access Memory (SRAM) devices, Dynamic Random Access Memory (DRAM) devices, Flash Memory devices, Magnetic Random Access Memory (MRAM) devices, Spin Torque Transfer Random Access Memory (STTRAM) devices, Resistive Random Access Memory (RRAM) devices, Phase Change Memory (PCM) devices, Ferroelectrics-based devices, and other memristive devices to discuss most potential candidates for in-memory computing. Thereafter, the workshop will host panel discussions to identify promising device technologies and other aspects of in-memory computing such as compatibility with Complementary Metal Oxide Semiconductor (CMOS) front end of line (FEOL), back end of line (BEOL), circuits and systems integration, and challenges with semiconductor manufacturing and packaging. The speakers and panelists will be selected from academia, semiconductor industry, federal research laboratories, and small and large business companies. The workshop will be organized on virtual platform and will consist of four technical sessions, one session on education and workforce development, and an open discussion on various other aspects such as role of open access platforms for semiconductor devices and manufacturing, and technology translation.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.