SHF: Small: Distributed Timing Analysis and Beyond

为了设计下一代复杂的微电子系统，需要在EDA（电子设计自动化）软件的设计上进行重大创新。时序分析是EDA的核心技术之一。它的任务是分析通过芯片各个部分传播的电信号的时序，从而使设计人员能够确定设计是否满足性能要求。鉴于芯片设计的复杂性不断增加，对数十亿晶体管电路时序的有效分析需求正迅速成为整个芯片设计过程的主要瓶颈。缓解此问题的典型方法是将芯片设计分解为几个分区，并使用单个计算机中的多个核心并行运行时序分析。对于今天的数十亿规模的设计，生成计时报告可能会消耗多达400 GB的内存。拟议的研究将通过解决这一需求来推进EDA的知识。它还将为其他领域增加新的知识，如通用分布式计算和网络优化，因为最终我们将需要解决分布式环境中的大规模优化问题。该项目的广泛影响包括微芯片设计技术的进步和下一代工程师的教育。微芯片是现代信息和通信系统的核心。所提出的研究改进了芯片设计技术，将造福于整个社会。新的研究成果将通过论文研究、课程设计、家庭作业和课堂教学传递给本科生和研究生。随着设计复杂性的不断增加，制造一台高端计算机既不划算，也不具有可扩展性。因此，最近的趋势推动了对EDA工具中的分布式时序分析（DTA）的需求。然而，迄今为止，DTA研究很少受到重视，仍然是一个关键问题。一个成功的分布式计时器不仅意味着更快地完成设计，还意味着有机会打破繁琐的设计层次结构，这有可能极大地提高设计的整体质量。分布式时序也是EDA要实现云友好需要克服的主要障碍之一，这被认为将带来设计生产力的下一个飞跃，并释放新的机会。本课题旨在构建一个高效、可扩展、鲁棒、安全的分布式时序分析系统。

In order to design next generations of complex microelectronic systems, major innovations in the design of EDA (Electronic Design Automation) software are needed. Timing analysis is a core EDA technology. It is the task of analyzing the timing of electrical signals propagating through various parts of the chip, thus allowing designers to determine if a design meets performance requirement. Given the ever-increasing chip design complexity, the need to efficiently analyze circuit timing with billions of transistors is quickly becoming the major bottleneck to the overall chip design process. A typical approach to mitigate this issue is to break down a chip design into several partitions and run timing analysis in parallel using the multiple cores in a single computer. For today's billion-scale designs, generating timing reports can consume up to 400 GB memory. The proposed research will advance knowledge in EDA by addressing this need. It will also add new knowledge to other fields such as general distributed computing and network optimization since ultimately we will need to solve large-scale optimization problems in distributed environment. The broader impacts of this project include microchip design technology advancement and the education of next generation engineers. Microchips are at the heart of modern information and communication systems. The proposed research improves chip design technology that will benefit the society at large. New research results will be passed on to undergraduate and graduate students through dissertation research, course projects, homework, and classroom teaching.As the design complexity continues to grow larger, building a high-end computer is neither cost-effective nor scalable. Therefore, recent trends are driving the requirement for distributed timing analysis (DTA) in EDA tools. However, DTA has by far received little research attention and remains a critical problem. A successful distributed timer means not only a faster path to design completion but also the chance of breaking cumbersome design hierarchies, which has the potential to tremendously improve the overall quality of design. Distributed timing is also one of the major hurdles to overcome for EDA to be cloud-friendly, which is believed to deliver the next leap of design productivity and unleash new opportunities. This research proposal proposes to build an efficient, scalable, robust and secure distributed timing analysis system.