SHF: Small: Distributed Timing Analysis and Beyond

为了设计下一代复杂的微电子系统，需要在 EDA（电子设计自动化）软件设计方面进行重大创新。时序分析是EDA的核心技术。它的任务是分析通过芯片各个部分传播的电信号的时序，从而使设计人员能够确定设计是否满足性能要求。鉴于芯片设计复杂性不断增加，有效分析数十亿个晶体管的电路时序的需求正迅速成为整个芯片设计过程的主要瓶颈。缓解此问题的典型方法是将芯片设计分解为多个分区，并使用单个计算机中的多个内核并行运行时序分析。对于当今数十亿规模的设计，生成时序报告可能会消耗高达 400 GB 的内存。拟议的研究将通过满足这一需求来推进 EDA 知识。它还将为其他领域（例如通用分布式计算和网络优化）添加新知识，因为最终我们需要解决分布式环境中的大规模优化问题。该项目的更广泛影响包括微芯片设计技术的进步和下一代工程师的教育。微芯片是现代信息和通信系统的核心。拟议的研究改进了芯片设计技术，将造福整个社会。新的研究成果将通过论文研究、课程项目、家庭作业和课堂教学传递给本科生和研究生。 随着设计复杂性不断增大，构建高端计算机既不具有成本效益，也不具有可扩展性。因此，最近的趋势正在推动 EDA 工具中对分布式时序分析 (DTA) 的需求。然而，DTA 迄今为止很少受到研究关注，仍然是一个关键问题。成功的分布式计时器不仅意味着更快地完成设计，而且有机会打破繁琐的设计层次结构，从而有可能极大地提高设计的整体质量。分布式时序也是 EDA 云友好型需要克服的主要障碍之一，这被认为将实现设计生产力的下一次飞跃并释放新的机遇。本研究提案提出建立一个高效、可扩展、鲁棒且安全的分布式时序分析系统。

In order to design next generations of complex microelectronic systems, major innovations in the design of EDA (Electronic Design Automation) software are needed. Timing analysis is a core EDA technology. It is the task of analyzing the timing of electrical signals propagating through various parts of the chip, thus allowing designers to determine if a design meets performance requirement. Given the ever-increasing chip design complexity, the need to efficiently analyze circuit timing with billions of transistors is quickly becoming the major bottleneck to the overall chip design process. A typical approach to mitigate this issue is to break down a chip design into several partitions and run timing analysis in parallel using the multiple cores in a single computer. For today's billion-scale designs, generating timing reports can consume up to 400 GB memory. The proposed research will advance knowledge in EDA by addressing this need. It will also add new knowledge to other fields such as general distributed computing and network optimization since ultimately we will need to solve large-scale optimization problems in distributed environment. The broader impacts of this project include microchip design technology advancement and the education of next generation engineers. Microchips are at the heart of modern information and communication systems. The proposed research improves chip design technology that will benefit the society at large. New research results will be passed on to undergraduate and graduate students through dissertation research, course projects, homework, and classroom teaching.As the design complexity continues to grow larger, building a high-end computer is neither cost-effective nor scalable. Therefore, recent trends are driving the requirement for distributed timing analysis (DTA) in EDA tools. However, DTA has by far received little research attention and remains a critical problem. A successful distributed timer means not only a faster path to design completion but also the chance of breaking cumbersome design hierarchies, which has the potential to tremendously improve the overall quality of design. Distributed timing is also one of the major hurdles to overcome for EDA to be cloud-friendly, which is believed to deliver the next leap of design productivity and unleash new opportunities. This research proposal proposes to build an efficient, scalable, robust and secure distributed timing analysis system.