RIA: Research in VLSI Circuit Layout

本研究针对超大规模积体电路的布局问题， 其中导线宽度在亚微米范围内并且晶体管密度 超过100万个芯片 这里的设计问题在计算上 难对付 私家侦探正在研究计算和算法 解决方法的各个方面，以及设计能够利用 设计问题的巨大复杂性。 研究课题有：（1） 直线型平面布置图设计的快速算法 模块;（2）用于直线设计的通道布线技术 单元;（3）通过基于制造标准的最小化方法 成本和复杂性，以及电路性能和可靠性;（4）新 多层拓扑通道布线算法;（5）自动化 （6）新的并行模拟方法 退火适用于解决这些设计问题。 本研究主要探讨半导体制程中IC布局的自动化问题， 导线宽度在亚微米范围内的情况下， 密度超过每个芯片一百万。 私家侦探有着新颖的想法， 这在解决自动化问题方面显示出希望。 校长 调查员是一个有前途的和有能力的年轻教授谁应该 为该领域做出重大贡献。

This research addresses the problem of VLSI circuit layout in the case where wire widths are in the sub-micron range and transistor density is beyond one million per chip. Design problems here are computationally intractable. The P.I. is studying both computational and algorithmic aspects of solution methods, and devising tools that can harness the enormous complexity of the design problems. Research topics are: (1) development of fast algorithms for floorplan designs with rectilinear modules; (2) channel routing techniques for designs with rectilinear cells; (3) via minimization methods based on criteria of manufacturing cost and complexity, and circuit performance and reliability; (4) new algorithms for multi-layer topological channel routing; (5) automation of leaf cell generation; and (6) new approaches to parallel simulated annealing applicable to solving these design problems. This research investigates the problem of automating IC layout in the case where wire widths are in the sub-micron range and transistor density is beyond one million per chip. The P.I. has novel ideas, which show promise in solving the automation problem. The principal investigator is a promising and competent young professor who should make significant contributions to the field.