RIA: Research in VLSI Circuit Layout

本研究解决了线宽在亚微米范围内，晶体管密度超过一百万个/片的超大规模集成电路布局问题。这里的设计问题在计算上是棘手的。私家侦探正在研究解决方法的计算和算法方面，并设计出能够驾驭设计问题的巨大复杂性的工具。研究课题有：(1)基于直线模块的平面布置图快速设计算法的开发；(2)直线型单元设计的通道路由技术；(3)基于制造成本和复杂性、电路性能和可靠性的最小化方法；(4)多层拓扑信道路由新算法；(5)叶细胞生成自动化；(6)适用于解决这些设计问题的并行模拟退火新方法。本研究探讨线宽在亚微米范围内，晶体管密度超过一百万个的情况下，IC的自动化布局问题。P.I.有新颖的想法，有望解决自动化问题。首席研究员是一位有前途和能力的年轻教授，应该在该领域做出重大贡献。

This research addresses the problem of VLSI circuit layout in the case where wire widths are in the sub-micron range and transistor density is beyond one million per chip. Design problems here are computationally intractable. The P.I. is studying both computational and algorithmic aspects of solution methods, and devising tools that can harness the enormous complexity of the design problems. Research topics are: (1) development of fast algorithms for floorplan designs with rectilinear modules; (2) channel routing techniques for designs with rectilinear cells; (3) via minimization methods based on criteria of manufacturing cost and complexity, and circuit performance and reliability; (4) new algorithms for multi-layer topological channel routing; (5) automation of leaf cell generation; and (6) new approaches to parallel simulated annealing applicable to solving these design problems. This research investigates the problem of automating IC layout in the case where wire widths are in the sub-micron range and transistor density is beyond one million per chip. The P.I. has novel ideas, which show promise in solving the automation problem. The principal investigator is a promising and competent young professor who should make significant contributions to the field.