RIA: Research in VLSI Circuit Layout

本研究针对布线宽度在亚微米范围内且晶体管密度超过百万个/片的VLSI电路布局问题进行研究。这里的设计问题在计算上很难处理。P.I.正在研究解决方法的计算和算法方面，并设计出能够利用设计问题的巨大复杂性的工具。主要研究内容包括：(1)直线型模块布局设计的快速算法的发展；(2)直线型单元设计的通道布线技术；(3)基于制造成本和复杂性以及电路性能和可靠性的最小化方法；(4)多层拓扑通道布线的新算法；(5)叶单元生成的自动化；(6)适用于解决这些设计问题的并行模拟退火法的新方法。本研究探讨了在布线宽度在亚微米范围内、晶体管密度超过每片一百万的情况下，IC布局的自动化问题。P.I.有新的想法，在解决自动化问题上显示出了希望。首席研究员是一位有前途的、有能力的年轻教授，他应该对这一领域做出重大贡献。

This research addresses the problem of VLSI circuit layout in the case where wire widths are in the sub-micron range and transistor density is beyond one million per chip. Design problems here are computationally intractable. The P.I. is studying both computational and algorithmic aspects of solution methods, and devising tools that can harness the enormous complexity of the design problems. Research topics are: (1) development of fast algorithms for floorplan designs with rectilinear modules; (2) channel routing techniques for designs with rectilinear cells; (3) via minimization methods based on criteria of manufacturing cost and complexity, and circuit performance and reliability; (4) new algorithms for multi-layer topological channel routing; (5) automation of leaf cell generation; and (6) new approaches to parallel simulated annealing applicable to solving these design problems. This research investigates the problem of automating IC layout in the case where wire widths are in the sub-micron range and transistor density is beyond one million per chip. The P.I. has novel ideas, which show promise in solving the automation problem. The principal investigator is a promising and competent young professor who should make significant contributions to the field.