Lazy Logic: Minimizing Activity to Reduce Processor Power Consumption

惰性逻辑：最大限度地减少活动以降低处理器功耗

• 批准号: 0702272
• 负责人: Mikko Lipasti
• 金额: --
• 依托单位: University of Wisconsin-Madison
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-05-01 至 2011-04-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0702272&HistoricalAwards=false
• 关键词: Lazy; Logic; Minimizing; Activity; Reduce

AbstractThe proposed research investigates lazy logic, a new design philosophy that has the potential to address many of the technological challenges that arise with nanometer-scale CMOS devices. Lazy logic rests on three principles: minimum clocking, which demands designs that use clocked storage only whenever absolutely required for correctness; pipeline avoidance, which encourages logic structures with multicycle delay paths and a scarcity of clocked latches; and lazy release, which promotes a lax resource allocation policy that avoids the power and delay overhead of utilization-efficient resource sharing by greedily holding onto resources across multiple invocations. When judiciously applied--either individually or in concert--these policies result in designs that are a better match for the realities of future nanometer technologies, since they reduce dynamic power, operating temperature, and relative static power. Furthermore, such designs are more tolerant of process variation, more likely to mask and less likely to latch and propagate combinational logic soft errors, and, due to their lower operating temperature and reduced activity rates, less prone to lifetime reliability problems. These benefits are realized with little to no detrimental effect on bandwidth or latency, and can result in surprising improvements in performance.The research will have a specific and significant impact on the logic design and computer architecture communities, since it requires development and analysis of interesting and representative workloads, realization of state-of-the-art simulation and design infrastructure, and invention of powerful and useful evaluation methodologies. Since most of the development and research work will be conducted by graduate students, industry and academia will benefit from well-educated and trained employees as well as direct technology transfer when students graduate and begin employment elsewhere. Finally, the techniques and methods created will be applied towards the development of increasingly powerful and ubiquitous computing devices whose utility will have a substantial impact on the productivity and creativity of countless end users.

AbstractThe拟议的研究调查懒惰的逻辑，一种新的设计理念，有可能解决许多纳米级CMOS器件出现的技术挑战。惰性逻辑依赖于三个原则：最小时钟，这要求设计只在绝对需要正确性的时候使用时钟存储;避免流水线，这鼓励逻辑结构具有多个延迟路径和时钟锁存器的稀缺性;和懒惰的释放，这促进了避免利用的功率和延迟开销的宽松的资源分配策略，通过在多个调用中保持资源的绿色，实现高效的资源共享。当明智地应用时--无论是单独应用还是协同应用--这些策略都会导致设计更好地匹配未来纳米技术的现实，因为它们降低了动态功率、工作温度和相对静态功率。此外，这种设计更能容忍工艺变化，更可能屏蔽并且不太可能锁存和传播组合逻辑软错误，并且由于其较低的操作温度和降低的活动率，不太容易出现寿命可靠性问题。这些好处的实现几乎没有对带宽或延迟的不利影响，并可能导致性能的惊人改善。该研究将对逻辑设计和计算机体系结构社区产生具体而重大的影响，因为它需要开发和分析有趣的和有代表性的工作负载，实现最先进的仿真和设计基础设施，并发明了强大而有用的评估方法。由于大部分开发和研究工作将由研究生进行，工业和学术界将受益于受过良好教育和培训的员工，以及学生毕业后开始在其他地方就业时的直接技术转让。最后，所创建的技术和方法将被应用于日益强大和无处不在的计算设备的开发，其实用性将对无数最终用户的生产力和创造力产生重大影响。