Lazy Logic: Minimizing Activity to Reduce Processor Power Consumption

摘要本研究探讨了惰性逻辑，这是一种新的设计理念，有可能解决纳米级CMOS器件出现的许多技术挑战。懒惰逻辑基于三个原则：最小时钟，这要求设计只在绝对需要正确性时使用时钟存储；管道避免，它鼓励逻辑结构具有多周期延迟路径和时钟锁存器的稀缺性；以及延迟释放，它促进了宽松的资源分配策略，通过在多个调用之间贪婪地占用资源，避免了高效利用资源共享的电力和延迟开销。当明智地应用这些策略时（无论是单独应用还是协同应用），这些策略会导致设计更好地匹配未来纳米技术的现实，因为它们降低了动态功率、工作温度和相对静态功率。此外，这种设计对工艺变化的容忍度更高，更有可能掩盖而不太可能锁定和传播组合逻辑软错误，并且由于其较低的工作温度和较低的活动率，更不容易出现寿命可靠性问题。实现这些好处对带宽或延迟几乎没有不利影响，并且可以带来令人惊讶的性能改进。这项研究将对逻辑设计和计算机体系结构社区产生具体而重要的影响，因为它需要开发和分析有趣的和有代表性的工作负载，实现最先进的模拟和设计基础设施，以及发明强大而有用的评估方法。由于大多数开发和研究工作将由研究生进行，工业界和学术界将受益于受过良好教育和训练的雇员，以及当学生毕业并开始在其他地方就业时的直接技术转让。最后，所创造的技术和方法将被应用于开发越来越强大和无处不在的计算设备，其效用将对无数最终用户的生产力和创造力产生重大影响。

AbstractThe proposed research investigates lazy logic, a new design philosophy that has the potential to address many of the technological challenges that arise with nanometer-scale CMOS devices. Lazy logic rests on three principles: minimum clocking, which demands designs that use clocked storage only whenever absolutely required for correctness; pipeline avoidance, which encourages logic structures with multicycle delay paths and a scarcity of clocked latches; and lazy release, which promotes a lax resource allocation policy that avoids the power and delay overhead of utilization-efficient resource sharing by greedily holding onto resources across multiple invocations. When judiciously applied--either individually or in concert--these policies result in designs that are a better match for the realities of future nanometer technologies, since they reduce dynamic power, operating temperature, and relative static power. Furthermore, such designs are more tolerant of process variation, more likely to mask and less likely to latch and propagate combinational logic soft errors, and, due to their lower operating temperature and reduced activity rates, less prone to lifetime reliability problems. These benefits are realized with little to no detrimental effect on bandwidth or latency, and can result in surprising improvements in performance.The research will have a specific and significant impact on the logic design and computer architecture communities, since it requires development and analysis of interesting and representative workloads, realization of state-of-the-art simulation and design infrastructure, and invention of powerful and useful evaluation methodologies. Since most of the development and research work will be conducted by graduate students, industry and academia will benefit from well-educated and trained employees as well as direct technology transfer when students graduate and begin employment elsewhere. Finally, the techniques and methods created will be applied towards the development of increasingly powerful and ubiquitous computing devices whose utility will have a substantial impact on the productivity and creativity of countless end users.