Lazy Logic: Minimizing Activity to Reduce Processor Power Consumption

摘要这项拟议的研究调查了懒惰逻辑，这是一种新的设计哲学，有可能解决纳米级CMOS器件所带来的许多技术挑战。惰性逻辑依赖于三个原则：最小时钟，它要求设计只有在绝对需要正确的时候才使用时钟存储；流水线避免，它鼓励具有多周期延迟路径的逻辑结构和时钟锁存器的稀缺；以及惰性释放，它促进宽松的资源分配策略，通过贪婪地跨多个调用持有资源来避免利用率高效的资源共享的电力和延迟开销。当明智地单独或联合应用时，这些政策会产生更符合未来纳米技术现实的设计，因为它们降低了动态功率、工作温度和相对静态功率。此外，这种设计对工艺变化的容忍度更高，更有可能屏蔽组合逻辑软错误，不太可能锁存和传播组合逻辑软错误，并且由于其较低的工作温度和较低的活动率，不太容易出现寿命可靠性问题。这项研究将对逻辑设计和计算机体系结构社区产生具体而重大的影响，因为它需要开发和分析感兴趣的具有代表性的工作负载，实现最先进的模拟和设计基础设施，并发明强大而有用的评估方法。由于大部分开发和研究工作将由研究生进行，工业界和学术界将受益于受过良好教育和培训的员工，以及当学生毕业并在其他地方就业时直接进行的技术转让。最后，所创造的技术和方法将被应用于日益强大和无处不在的计算设备的开发，其效用将对无数最终用户的生产力和创造力产生重大影响。

AbstractThe proposed research investigates lazy logic, a new design philosophy that has the potential to address many of the technological challenges that arise with nanometer-scale CMOS devices. Lazy logic rests on three principles: minimum clocking, which demands designs that use clocked storage only whenever absolutely required for correctness; pipeline avoidance, which encourages logic structures with multicycle delay paths and a scarcity of clocked latches; and lazy release, which promotes a lax resource allocation policy that avoids the power and delay overhead of utilization-efficient resource sharing by greedily holding onto resources across multiple invocations. When judiciously applied--either individually or in concert--these policies result in designs that are a better match for the realities of future nanometer technologies, since they reduce dynamic power, operating temperature, and relative static power. Furthermore, such designs are more tolerant of process variation, more likely to mask and less likely to latch and propagate combinational logic soft errors, and, due to their lower operating temperature and reduced activity rates, less prone to lifetime reliability problems. These benefits are realized with little to no detrimental effect on bandwidth or latency, and can result in surprising improvements in performance.The research will have a specific and significant impact on the logic design and computer architecture communities, since it requires development and analysis of interesting and representative workloads, realization of state-of-the-art simulation and design infrastructure, and invention of powerful and useful evaluation methodologies. Since most of the development and research work will be conducted by graduate students, industry and academia will benefit from well-educated and trained employees as well as direct technology transfer when students graduate and begin employment elsewhere. Finally, the techniques and methods created will be applied towards the development of increasingly powerful and ubiquitous computing devices whose utility will have a substantial impact on the productivity and creativity of countless end users.