SHF: Small: Reliable In-place Execution for Multicore Processors

微处理器行业已经过渡到芯片多处理器设计，其中通过持续的工艺扩展提供的额外片上资源致力于为每个die提供越来越多的处理器内核。由于单个芯片的功率是上限的，每个核心分配的总功率预算的一小部分不断缩小，因此很难或不可能设计出能够提供最终用户期望的性能改进的核心。与此同时，越来越小的设备更容易受到宇宙射线引起的瞬态误差的影响。由于这些原因，业界迫切需要新颖的微架构方法，这些方法可以提供高水平的单线程性能（执行延迟）和增强对软错误的弹性（可靠性），同时显著降低功耗。如果在节能、高性能多核构建模块的设计上没有显著的创新，未来纳米技术的持续设备缩放可能不再提供实用或性能方面的可观回报。因此，微处理器行业，乃至整个计算机行业，在维持维持了40年的以增长为基础的商业模式方面，面临着严峻的挑战。这项研究具有广泛的行业和经济范围的影响，因为它有助于解决或避免这些挑战。可靠就地执行（RIPE）项目研究基于指令就地执行概念的微体系结构方法。与指令以高频率遍历深度处理管道的传统设计不同，RIPE将指令分配到固定的执行站，在那里对其进行评估。这种方法通过最小化设备活动、避免流水线、复杂的控制逻辑、多端口存储结构和传统无序处理器核心的其他耗电组件，极大地提高了电源效率。RIPE还从本质上降低了单事件扰动（SEUs）的脆弱性，同时形成了一种有吸引力的低成本检测和恢复单事件瞬变（set）的基础。RIPE也非常适合简化指令获取，因为可以在多次循环迭代或解决条件控制流时重新激活原位指令，从而避免了从内存层次结构中获取指令的功率和性能成本，并消除了由于错误预测分支而造成的性能损失。RIPE内核也可以集群化和互联，以可扩展和节能的方式提供非常高的性能水平。这项研究如果成功，将导致处理器核心设计满足看似矛盾的目标，即适度的面积，低功耗，高指令级并行性（ILP），竞争频率，以及即使在本质上不可靠的未来技术中也能可靠运行。

The microprocessor industry has transitioned to chip-multiprocessor designs, where additional on-chip resources provided by continued process scaling are dedicated to providing more and more processor cores per die. Since power for a single die is capped, each core is allotted a shrinking fraction of the overall power budget, making it difficult or impossible to design a core that provides the performance improvements that end users expect. At the same time, ever smaller devices are more vulnerable to transient errors caused by cosmic rays. For these reasons, there is an urgent industry demand for novel microarchitectural approaches that deliver high levels of single-thread performance (execution latency) and increased resilience to soft errors (reliability), while dramatically reducing power consumption. Without dramatic innovations in the design of power-efficient, high-performance multicore building blocks, the continued device scaling of future nanometer technologies may no longer provide substantial returns in utility or performance. As a result, the microprocessor industry, and by extension, the computer industry as a whole, face a serious challenge in maintaining the growth-based business model that has sustained them for four decades. This research has broad industry- and economy-wide impact since it helps to address or avert these challenges. The Reliable In-Place Execution (RIPE) project investigates microarchitectural approaches based on the concept of in-place execution of instructions. In contrast to conventional designs where instructions traverse deep processing pipelines at high frequency, RIPE assigns an instruction to a fixed execution station where it is evaluated in place. This approach dramatically improves power efficiency by minimizing device activity and avoiding pipelining, complex control logic, multiported storage structures, and other power-hungry components of traditional out-of-order processor cores. RIPE also inherently reduces vulnerability to single-event upsets (SEUs), while forming an attractive substrate for low-cost detection of and recovery from single-event transients (SETs). RIPE is also uniquely suited for streamlining instruction fetch, since the in-place instructions can be reactivated for multiple loop iterations or to resolve conditional control flow, avoiding the power and performance costs of fetching instructions from the memory hierarchy, and eliminating performance penalties due to mispredicted branches. RIPE cores can also be clustered and interconnected to provide very high levels of performance in a scalable and power-efficient manner. The proposed research, if successful, will lead to processor core designs that meet the seemingly contradictory objectives of modest area, low power consumption, high instruction-level parallelism (ILP), competitive frequency, and reliable operation even in inherently unreliable future technologies.