Heterogeneous Interconnect Stitching Technology (HIST) For High-Performance Computing Systems

现代生活的各个方面（如经济、健康和通讯）都依赖于先进的电子技术。因此，发现提高电子系统性能的方法将直接导致生活质量的提高。此外，提高电子产品的能源效率直接影响社会，因为它减少了现代数据中心的碳足迹，增加了无处不在的移动设备的使用寿命。本项目旨在通过探索一种基于异构互连拼接的新型电子集成概念来提高电子系统的性能和能源效率。提出的集成方法的主要创新是使用封装表面的缝合芯片在组装的骰子之间形成密集和低能量的互连。此外，组装的芯片使用多高度和多间距可压缩微互连互连，这是高密度机械柔性互连，可实现所有芯片之间的鲁棒互连。为了实现我们的目标，我们研究了以下基础研究课题：1)利用互连拼接分析多模组件中的电源噪声；2)实验演示了使用互连拼接的2x2芯片阵列的组装；3)提取高达50 GHz的可压缩微互连的频率相关寄生。所有的研究都将在佐治亚理工学院进行，佐治亚理工学院是美国国家科学基金会支持的国家纳米技术协调基础设施项目的一个节点。这使我们能够轻松地向K-12学生展示这项研究，并鼓励他们接受科学和工程教育。建议的研究也将涉及研究生和本科生进行多学科的研究，包括电气工程，机械工程和化学工程。这样的研究经验将加强他们的教育，并更好地为学生在工业中工作做好准备，因为他们已经对不同学科如何在电子系统中相互作用有了基本的了解。电子计算系统的性能和功耗越来越受到互连的影响。提出的异构互连拼接技术（HIST）可以大大缩短组件之间的互连长度；从而以降低的每比特能量提供更高的带宽密度。此外，所提出的研究将使有源器件（光子，逻辑，存储器等）的集成非常接近（即面对面键合）；从而大大减少电寄生和提高互连密度。但是，由于组装封装的功率密度增加，所提出的集成方法可能会加剧功率传输方面的挑战。因此，提出的研究的智力价值是双重的。首先，提出的研究将在提出的异构集成方法中发展对输电网络设计的基本理解，以最大限度地减少寄生引起的电压降和开关噪声作为几个技术参数的函数。其次，提出的研究将通过实验证明实现低功耗和高性能计算系统的关键互连和组装技术。实验工作将特别侧重于开发一个2x2的骰子阵列，使用缝合芯片相互连接，并表征高达50 GHz的HIST互连通道。实验研究还将探索多高度、多螺距可压缩微互连的鲁棒性和高成品率批量制造及其机械可靠性。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Every aspect of modern life (e.g., economy, health, and communication) is dependent on advanced electronics. As such, discovering methods that improve the performance of electronic systems will directly lead to improvements in quality of life. Moreover, improving the energy efficiency of electronics directly impacts society as it reduces the carbon footprint of modern data centers and increases the lifetime of ubiquitous mobile devices. This project aims to improve both the performance and energy efficiency of electronic systems by exploring a new electronic integration concept based on heterogeneous interconnect stitching. The principle innovation in the proposed integration approach is the use of stitch chips on the surface of a package to form dense and low-energy interconnects between the assembled dice. The assembled chips, moreover, are interconnected using multi-height and multi-pitch compressible micro-interconnects, which are high density mechanically flexible interconnects that enable robust interconnection between all chips. To accomplish our objectives, the following fundamental research topics are investigated: 1) analysis of the power supply noise in multi-die assemblies using interconnect stitching; 2) experimentally demonstrating the assembly of a 2x2 array of chips using interconnect stitching; and 3) extracting the frequency-dependent parasitics of the compressible micro-interconnects up to 50 GHz. All research will be performed at Georgia Tech, which is one of the nodes within the NSF supported National Nanotechnology Coordinated Infrastructure program. This enables us to easily expose K-12 students to this research and encourage them to pursue science and engineering education. The proposed research will also involve the graduate and undergraduate students conducting the research with multiple disciplines that include electrical engineering, mechanical engineering, and chemical engineering. Such research experience will enhance their education and better prepares students to work in industry because they would already have a fundamental understanding of how different disciplines interact with each other in electronic systems.The performance and power dissipation of electronic computing systems have become increasingly dominated by interconnections. The proposed Heterogeneous Interconnect Stitching Technology (HIST) can greatly reduce interconnect length between components; thereby offering higher bandwidth density at reduced energy per bit. Moreover, the proposed research will enable the integration of active devices (photonic, logic, memory, etc.) in very close proximity (i.e., face-to-face bonding); thereby greatly reducing electrical parasitics and improving interconnect densities. But, the proposed integration approach may exacerbate the challenges in power delivery due to increased power density of the assembled package. As a result, the intellectual merit of the proposed research is twofold. First, the proposed research will develop fundamental understanding of the power delivery network design in the proposed heterogeneous integration approach to minimize parasitics-induced voltage drops and switching noise as a function of several technology parameters. Second, the proposed research will experimentally demonstrate the key interconnect and assembly technologies that will enable low-power and high-performance computing systems. The experimental effort will specifically focus on developing a 2x2 array of dice interconnected using stitch chips and the characterization of the HIST interconnect channels up to 50 GHz. The experimental research will also explore robust and high-yield batch-scale fabrication of multi-height and multi-pitch compressible micro-interconnects as well as their mechanical reliability.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.