Investigation of the long-term degradation of the high-frequency behavior of SiGe heterojunction bipolar transistors and circuits

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Recent technology development of silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) has led to maximum operating frequencies of 500 GHz and beyond at 1.6 V breakdown voltage (BVCEO) even for industry prototyping processes. BiCMOS technology, resulting from combining high-speed HBT circuits with moderate-cost digital CMOS, and SiGe HBT performance projections far into the THz region, have spurred increasing interest in utilizing the millimeter (mm)-wave and THz frequency spectrum for compact commercial electronic applications. Such high performance comes though at the cost of very high current densities, high self-heating, and low breakdown voltages which are presently assumed to limit the output power at high frequencies. Pushing the device performance boundaries though, the above mentioned effects can lead to an acceleration of device degradation. So far, the latter is only described by a static safe operating area (SOA), using a static base current that is mostly irrelevant for HF circuit design, while information on the associated loss of performance under high-frequency (HF) operation has not been available. In the first phase of this project, it was demonstrated that SiGe HBTs are extremely rugged and can be operated far beyond the foundry recommended SOA before a measurable degradation occurs. This implies a potential for achieving at high frequencies significantly larger output power than presently assumed. Also, for the measured device geometry, experimental evidence has been found for degradation of various HF performance related parameters due to dynamic stress. Therefore, the main objectives of this second phase of the project are: (i) Systematic experimental evaluation of dynamic degradation in advanced SiGe HBTs as function of geometry and frequency for investigating the physical origin of the observed degradation. (ii) Exploration of the achievable high-frequency output power limit and associated degradation related trade-offs during circuit design. (iii) Compact modeling of the observed degradation effects and development of an approach for estimating degradation and reliability during HF circuit simulation and design. (iv) Experimental stress tests of selected HF circuit building blocks and comparison of their performance degradation over time with circuit simulation. This work will span over a wide frequency range (10 GHz to 180 GHz) and will go significantly beyond conventional static reliability tests. Its results will enable HF circuit design including degradation effects of the relevant transistor parameters.