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A STUDY OF ULTRASMALL DEVICE CONTAINING NANOMETER-CONTROLLED Si-Ge HETEROLAYER

含纳米控制Si-Ge异质层的超小型器件的研究

基本信息

批准号：
04452167
负责人：
MUROTA Junichi
金额：
$ 3.71万
依托单位：
TOHOKU UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (B)
财政年份：
1992
资助国家：
日本
起止时间：
1992 至 1993
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-04452167/
关键词：
Silicon Silicon-Germanium Heterostructure Heterodevice Ultrasmall Device CVD MOSFET

项目摘要

The object of this research is to construct the fabrication process of a high performance ultrasmall device containing nanometer controlled Si_<1-x>Ge_x heterolayr. The research results are summarized as follows.(1) A very low-temperature epitaxial growth process of the Si/Si_<1-x>Ge_x/Si heterostructure with atomically flat surfaces and interfaces for Ge fractions on Si(100) has been achieved under the cleanest possible reaction and interfaces for Ge fracions on Si(100) has been achieved under the cleanest possible reaction environment of SiH_4, GeH_4 and H_2 or Ar using an ultraclean hot-wall low-pressure CVD system. A relatively lower deposition temperatures were suitable for higher Ge fractions in order to prevent island growth of thelayrs during deposition. Atomically flat surfaces and interfaces for the heterostructure containing Si_<0.8>Ge_<0.2>, Si_<0.5>Ge_<0.5> and Si_<0.3>Ge_<0.7> layrs were obtained by deposition at 550, 500 and 450ﾟC, respectively.(2) MOSFET's were fabricated at temparetures below 700ﾟC on the 10nm-thick Si/7nm-thick Si_<1-x>Ge_x/Si heterostructure using a self-alligned Si gate process. A high performance Si_<0.5>Ge_<0.5>-channel MOSFET has been achieved with a large mobility enhancement of about 70% at 300K and over 150% at 77K compared with that of a MOSFET without SiGe-channel.(3) In-situ B doping control of Si_<1-x>Ge_x layr was achieved in the range of 3x10^<17>-2x10^<20>cm^<-3>. It was found that Hall mobility has a minimum value for Si_<0.75>Ge_<0.25> film, and the mobility of the strained Si_<0.75>Ge_<0.25> film is neary equal to that of the unstrained one.(4) In-sity B doped selective SiGe epitaxial growth were achieved at 550ﾟC.Using this selective film, high performance self-aligned ultrashallow junction was formed with a low level reverse current density, the range of 10^<-10>A/cm^2. As a result, the overlap control between gate and source/drain and suppression of short channel effects in ultrasmall MOSFET can be improved.

本研究的目的是构建一种包含纳米控制的Si_(1-x)&Ge_x异质结的高性能超小型器件的制备工艺。(1)利用超薄热壁低压CVD系统，在最清洁的反应条件下，实现了Si/Si_&lt；1-x&Gt；Ge_x/Si异质结构的超低温外延生长过程，并实现了Si(100)上Ge组分的界面和SiH_4、GeH_4、H_2或Ar的界面的超薄外延生长。较低的沉积温度有利于较高的Ge组分，以防止沉积过程中Ge层的岛状生长。在5 5 0、5 0 0和4 5 0ﾟC的温度下，分别在10 nm厚的Si/7 nm厚的Si/1-x&gt；1-x&gt；Si&lt；0.3&gt；Ge&lt；0.7&gt；采用自对准硅栅工艺的Ge_x/Si异质结。获得了高性能的Si&lt；0.5；Ge_t；0.5&gt；沟道MOSFET，与无SiGe沟道的MOSFET相比，其迁移率在300K时提高了约70%，在77K时提高了150%以上。(3)实现了3×10^；17&gt；-2×10^&lt；20&gt；cm^&lt；-3&gt；结果表明，Si_(0.75)Ge_(0.75)Ge_(0.25)薄膜的霍尔迁移率有一个极小值，应变Si_(0.75)Ge_(0.75)Ge_(0.25)薄膜的霍尔迁移率与无应变Si_(0.75)Ge_(0.25)薄膜的迁移率几乎相等。(4)在550ﾟC下实现了浓度B掺杂的选择性SiGe外延生长，形成了低反向电流密度的高性能自对准超低结。A/cm^2。因此，可以改善超小MOSFET中栅和源漏之间的重叠控制和对短沟效应的抑制。