HERMES: High dEnsity Silicon GeRManium intEgrated photonicS
HERMES: High dEnsity Silicon GeRManium intEgrated photonicS
批准号:
EP/K02423X/1
负责人:
Frederic Gardes
金额:
$12.76万
依托单位国家:
英国
项目类别:
Research Grant
财政年份:
2013
资助国家:
英国
项目状态:
已结题
起止时间:
2013 至 --
中文摘要
HERMES的目标是实现Ge和GeSi材料平台,该平台将主要用于维持光学互连电路,以满足摩尔定律延续到2020年以后的密度、数据速率和功耗要求。ITRS路线图显示,在当前技术下,2020年以后微处理器输入/输出所需的电引脚数量将达到3000个左右。这种饱和与不断增加的延迟和有限的片上时钟速度是一个瓶颈,高密度光互连必须缓解。为了满足ITRS 2020的目标,目标很明确,片外IO能力超过100tb /s,整个光链路的功耗为100fJ/bit。这项工作提出了一个解决这个问题的方法,并提供了一种新的制造方法,超越了标准平面硅光子电路的能力。为此,我们的目标是开发一种基于绝缘体上局部锗/硅化合物的多层光学平台,该平台与微米尺寸的腔基结构的制造兼容,从而实现调制器和探测器等设备。也可以设想基于III/V材料或掺杂锗的激光源的增长,但这超出了本提案的范围。提出的平台将建立一种制造和演示微米级光学器件的方法,以解决光学片上互连所需的大规模光学集成所需的三维、高密度、低电压和低电容要求。
英文摘要
HERMES is aimed at realising a Ge and GeSi material platform that will be aimed primarily at sustaining optical interconnect circuits to meet the density, data rate and power consumption requirements for the continuation of Moore's law beyond 2020. The ITRS roadmap shows a saturation of the number of electrical pins required for input/output on microprocessors beyond 2020 to about 3000 with current technology. This saturation with an ever increasing latency and a limited on-chip clock speed is a bottle neck that high density optical interconnects have to alleviate. To meet the ITRS 2020 goals the target is clear, with over 100 Tb/s off chip IO capability and power consumption for an entire optical link on the order of 100fJ/bit.This work proposes a solution to this problem and provides a novel means of fabrication to go beyond the capabilities of standard planar silicon photonics circuits. To do so we aim to develop a multilayer optical platform based on localised Germanium/Silicon compounds on insulator compatible with the fabrication of micrometre sized cavity based structures enabling devices such as modulators and detectors. The growth of laser sources based on III/V materials or doped Germanium could also be envisioned but this is beyond the scope of this proposal. The proposed platform will establish a means to fabricate and demonstrate micrometre scale optical devices fit to tackle the 3 dimensional, high density, low voltage and low capacitance requirements needed for very large scale optical integration necessary for optical on chip interconnects.
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DOI:
10.1063/1.5066996
发表时间:
2019-04
期刊:
Applied Physics Letters
影响因子:
4
作者:
[M. Clementi;K. Debnath;M. Sotto;A. Barone;A. Khokhar;T. D. Bucio;S. Saito;F. Gardes;D. Bajoni;M. Galli]
通讯作者:
M. Clementi;K. Debnath;M. Sotto;A. Barone;A. Khokhar;T. D. Bucio;S. Saito;F. Gardes;D. Bajoni;M. Galli
DOI:
10.1364/ol.43.001251
发表时间:
2018-03-15
期刊:
OPTICS LETTERS
影响因子:
3.6
作者:
[Bucio, Thalia Dominguez, Khokhar, Ali Z., Gardes, Frederic Y.]
通讯作者:
Gardes, Frederic Y.
Single Crystal SiGe-on-insulator
绝缘体上单晶硅锗
DOI:
--
发表时间:
2015
期刊:
影响因子:
--
作者:
[C. G. Littlejohns]
通讯作者:
C. G. Littlejohns
DOI:
10.1364/cleo_si.2018.stu3f.2
发表时间:
2018
期刊:
影响因子:
--
作者:
[Clementi M]
通讯作者:
Clementi M
Near- and mid- infrared group IV photonics
近红外和中红外 IV 族光子学
DOI:
--
发表时间:
2016
期刊:
影响因子:
--
作者:
[C. G. Littlejohns]
通讯作者:
C. G. Littlejohns
共 7 条
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