Ultra-Parallel and Ultra-High-Speed Architecture for Ultimate Integration

超并行、超高速架构，实现终极集成

• 批准号: 07248102
• 负责人: KAMEYAMA Michitaka
• 金额: $ 111.04万
• 依托单位: Tohoku University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research on Priority Areas
• 财政年份: 1995
• 资助国家: 日本
• 起止时间: 1995 至 1998
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-07248102/
• 关键词: Logic-In-Memory VLSI; Current-Mode Multiple-Valued Integrated Circuits; Nueron MOS; Functional Memory; Self-Timed Urtra-Highlv-Parallel Architecture; Moving Picture Compression; Higher-Radix Arithmetic Circuits; Neural Network; 知能集積システム; 自己タイミング超

We proposed fundamental technologies which make possible many applications such as multimedia systems, highly-safe intelligent integrated systems and home service robots. In comarison with conventional technogies, the performance improvement sometimes becomes the order of hundred-times larger. The developed new-concepts are shown below :(1) A new logic-in-memory VLSI architecture based on multiple-valued floating-gate pass logic is proposed to solve communication bottleneck between memory units and arithmetic logic units. Since multiple-valued pass transistor network is realized by multiple-valued threshold literal and pass switch functions, the logic-in-memory VLSI can be implemented easily with a very simplecircuit. The performance improvement will be about fifty times higher than the conventional circuit architecture. Multiple-valued current-mode circuit technology will be merged with the logic-in-memory architecture in near future. The application is a new FPGA architecture with bo … More ttleneck-free communication, and a power control technique on memory and, arithmetic and logic units.(2) A design methodology for neuron MOS logic combined with CMOS logic is proposed. Also, a system design environment is developed based on Soft-Core processor and a low power system architecture Power-Pro for designing flexible architectures.(3) A new functional memory architecture is developed for computing inside memory devices. Several LSIs suited for vector quantization have been fabricated, which can be applied to real-time image compression.(4) A novel and unique ULSI system architecture based upon the data-driven parallel processing scheme and the self-timed super-pipelined hardware is established. ULSI chips realized by using 0.25 micron 4 ML technology can process video signal operations at 8.6 BOPS (1.2W@2.5V).(5) A design methods of fault-tolerant neural networks are discussed. For mutually coupled neural networks. some multiplicated techniques are developed. For feedforward neural networks, the application of relearning makes the MTTF greatly improved.(6) Design of a neural computer architecture for intelligent processing and its computer architecture are developed. Also, implementation methods of the fundamental software such as operating system and the middleware on semiconductor chips are investigated.(7) Beyond-binary computing algorithms for addition. multiplication, division, CORDIC, real/complex arithmetic. etc. are developed. Their impacts on high-performance processor design are demonstrated using binary/multi-valued/set-valued logic LSI technologies.(8) Smart image sensors for high-speed and low-power moving picture compression architecture are developed. It is demonstrated that the on-sensor image compression is particularly useful for these purposes through actual CMOS sensor LSI chip implementation. Less

我们提出了使多媒体系统、高安全智能集成系统和家庭服务机器人等许多应用成为可能的基础技术。与传统技术相比，性能提升有时会达到数百倍的数量级。所开发的新概念如下：(1)提出了一种基于多值浮栅传输逻辑的新型存储器逻辑VLSI架构，以解决存储器单元和算术逻辑单元之间的通信瓶颈。由于多值传输晶体管网络是通过多值阈值文字和传输开关功能实现的，因此可以用非常简单的电路轻松实现存储器中逻辑VLSI。性能提升将比传统电路架构提高约五十倍。多值电流模式电路技术将在不久的将来与内存中逻辑架构合并。该应用是一种新型FPGA架构，具有无瓶颈通信，以及存储器和算术逻辑单元的功耗控制技术。(2)提出了神经元MOS逻辑与CMOS逻辑相结合的设计方法。此外，还开发了基于Soft-Core处理器和低功耗系统架构Power-Pro的系统设计环境，用于设计灵活的架构。(3)开发了一种新的功能存储架构，用于存储设备内部的计算。已经制作了多种适合矢量量化的LSI，可应用于实时图像压缩。(4)建立了基于数据驱动并行处理方案和自定时超级流水线硬件的新颖独特的ULSI系统架构。采用0.25微米4 ML技术实现的ULSI芯片可以在8.6 BOPS(1.2W@2.5V)下处理视频信号运算。(5)讨论了容错神经网络的设计方法。对于相互耦合的神经网络。开发了一些多重技术。对于前馈神经网络来说，再学习的应用使得MTTF大大提高。(6)开发了一种用于智能处理的神经计算机体系结构的设计及其计算机体系结构。并研究了操作系统、中间件等基础软件在半导体芯片上的实现方法。(7)超二进制加法计算算法。乘法、除法、CORDIC、实数/复数算术。等被开发出来。它们对高性能处理器设计的影响通过二进制/多值/集值逻辑LSI技术得到证明。(8)开发了用于高速和低功耗运动图像压缩架构的智能图像传感器。通过实际的 CMOS 传感器 LSI 芯片实现，证明传感器上图像压缩对于这些目的特别有用。较少的

项目成果

Tkahiro Hanyu: "Design of a One-Transistor-Cell Multiple-Valued CAM"IEEE Journal of Solid-State Circuits. Vol.31. 1669-1674 (1996)

Tkahiro Hanyu：“单晶体管单元多值 CAM 的设计”IEEE 固态电路杂志。

羽生貴弘: "ディジットパラレル多値CAM構成と評価"電子情報通信学会論文誌D-I. J81-D-I. 151-156 (1998)

Takahiro Hanyu：“数字并行多值 CAM 配置和评估”IEICE Transactions D-I 151-156 (1998)。

Tatsuo Higuchi: "Multiplex computing system based on set-valued logic"Computers & Electrical Engineering. Vol.23. 381-392 (1997)

Tatsuo Higuchi：“基于集值逻辑的复用计算系统”计算机

G. Chakraborty: "Combining Local Representative Networks"Intl Symposium on Nonlinear Theory and its Applications. 153-156 (1996)

G. Chakraborty：“结合局部代表网络”非线性理论及其应用国际研讨会。

Shoichi Noguchi: "Next generation network technology and future strategy for its development"Joho Kanri journal. Vol. 42. (2000)

Shoichi Noguchi：“下一代网络技术及其未来发展战略”Joho Kanri 杂志。