Ultra-Parallel and Ultra-High-Speed Architecture for Ultimate Integration

我们提出了使多媒体系统、高度安全的智能集成系统和家庭服务机器人等许多应用成为可能的基础技术。与传统技术相比，性能改进有时会提高数百倍。(1)为解决存储单元和算术逻辑单元之间的通信瓶颈，提出了一种基于多值浮栅通路逻辑的存储器中逻辑VLSI结构。由于多值通路晶体管网络是由多值阈值文字和通路开关函数实现的，所以用非常简单的电路可以很容易地实现存储器中逻辑的VLSI。性能改进将比传统电路结构高出约50倍。在不久的将来，多值电流模式电路技术将与存储器中逻辑结构相融合。该应用是一种采用bo…的新型fpga体系结构。提出了一种神经MOS逻辑与CMOS逻辑相结合的设计方法。开发了基于软核处理器和低功耗体系结构Power-Pro的系统设计环境，设计了灵活的体系结构。(3)提出了一种新的面向存储器件内部计算的功能存储体系结构。建立了一种新颖独特的基于数据驱动并行处理方案和自定时超流水线硬件的超大规模集成电路系统结构。采用0.25微米4ML工艺实现的ULSI芯片可以处理8.6bps(1.2W@2.5V)的视频信号。(5)讨论了容错神经网络的设计方法。用于相互耦合的神经网络。发展了一些倍增技术。对于前馈神经网络，再学习的应用使得平均传递函数有了很大的提高。(6)设计了一种智能处理的神经计算机体系结构及其计算机体系结构。研究了操作系统、中间件等基础软件在半导体芯片上的实现方法。(7)加法超二进制计算算法。乘法、除法、CORDIC、实数/复数运算。等发展起来的。利用二值/多值/集值逻辑LSI技术论证了它们对高性能处理器设计的影响。(8)开发了适用于高速低功耗运动图像压缩体系结构的智能图像传感器。通过实际的CMOS型传感器LSI芯片的实现，证明了传感器上的图像压缩对于这些目的是特别有用的。较少

We proposed fundamental technologies which make possible many applications such as multimedia systems, highly-safe intelligent integrated systems and home service robots. In comarison with conventional technogies, the performance improvement sometimes becomes the order of hundred-times larger. The developed new-concepts are shown below :(1) A new logic-in-memory VLSI architecture based on multiple-valued floating-gate pass logic is proposed to solve communication bottleneck between memory units and arithmetic logic units. Since multiple-valued pass transistor network is realized by multiple-valued threshold literal and pass switch functions, the logic-in-memory VLSI can be implemented easily with a very simplecircuit. The performance improvement will be about fifty times higher than the conventional circuit architecture. Multiple-valued current-mode circuit technology will be merged with the logic-in-memory architecture in near future. The application is a new FPGA architecture with bo … More ttleneck-free communication, and a power control technique on memory and, arithmetic and logic units.(2) A design methodology for neuron MOS logic combined with CMOS logic is proposed. Also, a system design environment is developed based on Soft-Core processor and a low power system architecture Power-Pro for designing flexible architectures.(3) A new functional memory architecture is developed for computing inside memory devices. Several LSIs suited for vector quantization have been fabricated, which can be applied to real-time image compression.(4) A novel and unique ULSI system architecture based upon the data-driven parallel processing scheme and the self-timed super-pipelined hardware is established. ULSI chips realized by using 0.25 micron 4 ML technology can process video signal operations at 8.6 BOPS (1.2W@2.5V).(5) A design methods of fault-tolerant neural networks are discussed. For mutually coupled neural networks. some multiplicated techniques are developed. For feedforward neural networks, the application of relearning makes the MTTF greatly improved.(6) Design of a neural computer architecture for intelligent processing and its computer architecture are developed. Also, implementation methods of the fundamental software such as operating system and the middleware on semiconductor chips are investigated.(7) Beyond-binary computing algorithms for addition. multiplication, division, CORDIC, real/complex arithmetic. etc. are developed. Their impacts on high-performance processor design are demonstrated using binary/multi-valued/set-valued logic LSI technologies.(8) Smart image sensors for high-speed and low-power moving picture compression architecture are developed. It is demonstrated that the on-sensor image compression is particularly useful for these purposes through actual CMOS sensor LSI chip implementation. Less