Ultra-Parallel and Ultra-High-Speed Architecture for Ultimate Integration

我们提出的基础技术使多媒体系统、高度安全的智能集成系统和家庭服务机器人等许多应用成为可能。与传统技术相比，性能改进有时会达到数百倍的数量级。(1)提出了一种基于多值浮门通逻辑的内存逻辑VLSI架构，解决了存储单元与算术逻辑单元之间的通信瓶颈。由于多值通通晶体管网络是通过多值阈值文字和通通开关功能来实现的，因此内存逻辑VLSI可以用非常简单的电路轻松实现。性能改进将比传统电路架构高出约50倍。在不久的将来，多值电流模式电路技术将与内存逻辑架构相融合。该应用是一种新的FPGA体系结构，具有更大的无瓶颈通信，并在存储器和算术和逻辑单元上采用功率控制技术。(2)提出了一种神经元MOS逻辑与CMOS逻辑相结合的设计方法。此外，还开发了基于软核处理器和低功耗系统架构power - pro的系统设计环境，用于设计灵活的体系结构。(3)提出了一种新的功能存储架构，用于存储设备内部的计算。制备了几种适合矢量量化的lsi，可应用于实时图像压缩。(4)基于数据驱动并行处理方案和自定时超流水线硬件，建立了一种新颖独特的ULSI系统架构。采用0.25微米4毫升技术实现的ULSI芯片可以处理8.6 BOPS的视频信号操作（1.2W@2.5V）。(5)讨论了容错神经网络的设计方法。对于相互耦合的神经网络。开发了一些复合技术。对于前馈神经网络，再学习的应用使MTTF得到了很大的提高。(6)设计了一种用于智能处理的神经计算机体系结构及其计算机体系结构。同时，研究了操作系统和中间件等基础软件在半导体芯片上的实现方法。(7)加法的超二进制计算算法。乘法，除法，CORDIC，实数/复数算术。等发展起来。它们对高性能处理器设计的影响使用二进制/多值/集值逻辑LSI技术进行了演示。(8)开发了用于高速低功耗运动图像压缩架构的智能图像传感器。通过实际CMOS传感器LSI芯片的实现，证明了传感器上的图像压缩对这些目的特别有用。少

We proposed fundamental technologies which make possible many applications such as multimedia systems, highly-safe intelligent integrated systems and home service robots. In comarison with conventional technogies, the performance improvement sometimes becomes the order of hundred-times larger. The developed new-concepts are shown below :(1) A new logic-in-memory VLSI architecture based on multiple-valued floating-gate pass logic is proposed to solve communication bottleneck between memory units and arithmetic logic units. Since multiple-valued pass transistor network is realized by multiple-valued threshold literal and pass switch functions, the logic-in-memory VLSI can be implemented easily with a very simplecircuit. The performance improvement will be about fifty times higher than the conventional circuit architecture. Multiple-valued current-mode circuit technology will be merged with the logic-in-memory architecture in near future. The application is a new FPGA architecture with bo … More ttleneck-free communication, and a power control technique on memory and, arithmetic and logic units.(2) A design methodology for neuron MOS logic combined with CMOS logic is proposed. Also, a system design environment is developed based on Soft-Core processor and a low power system architecture Power-Pro for designing flexible architectures.(3) A new functional memory architecture is developed for computing inside memory devices. Several LSIs suited for vector quantization have been fabricated, which can be applied to real-time image compression.(4) A novel and unique ULSI system architecture based upon the data-driven parallel processing scheme and the self-timed super-pipelined hardware is established. ULSI chips realized by using 0.25 micron 4 ML technology can process video signal operations at 8.6 BOPS (1.2W@2.5V).(5) A design methods of fault-tolerant neural networks are discussed. For mutually coupled neural networks. some multiplicated techniques are developed. For feedforward neural networks, the application of relearning makes the MTTF greatly improved.(6) Design of a neural computer architecture for intelligent processing and its computer architecture are developed. Also, implementation methods of the fundamental software such as operating system and the middleware on semiconductor chips are investigated.(7) Beyond-binary computing algorithms for addition. multiplication, division, CORDIC, real/complex arithmetic. etc. are developed. Their impacts on high-performance processor design are demonstrated using binary/multi-valued/set-valued logic LSI technologies.(8) Smart image sensors for high-speed and low-power moving picture compression architecture are developed. It is demonstrated that the on-sensor image compression is particularly useful for these purposes through actual CMOS sensor LSI chip implementation. Less