Development of a Chip Family for Ultra-Highly-Parallel Multiple-Valued Integrated Circuits and Its Applications

在这项研究中，详细考虑了高并行算术电路、内存中逻辑VLSI体系结构以及低功耗、高速多值集成电路的硬件算法。建立了基于电平复用的多值集成电路的实用性，为开发多值芯片族的基础技术奠定了基础。本文的主要研究成果如下：1.高并行多值算术逻辑电路的设计提出了三种最终并行多值运算电路的代码分配方法。当通过输入和输出符号之间的映射关系给出k元运算的功能规范时。(1)基于稀疏矩阵的Reed-Muller展开，(2)分块理论，(3)基于热码的分层编码分配等。电流型多值集成电路的研制--双轨…差分逻辑电路的应用更多的输入使输入电压摆幅较小，从而在较低的电源电压下获得较高的驱动能力。进一步考虑了电路的优化设计，在降低功耗的前提下提高了系统的性能。显然，使用两个电源电压对改进非常有用。此外，我们还提出了多值VLSI的异步和自检设计方法。从而为下一代多值VLSI系统提供基础技术。提出了一种基于多值浮栅MOS通路逻辑的新型存储器中逻辑VLSI体系结构，以解决存储器与逻辑模块之间的通信瓶颈问题。多值排序数据由浮栅MOS晶体管的阈值电压表示，从而有效地使用单个浮栅MOS晶体管来合并阈值文字和通过开关功能。作为存储器中逻辑VLSI的典型例子，研制了一种全并行幅度比较器。与相应的二进制实现相比，该VLSI的性能提高了约26倍。此外，它的有效芯片面积和功耗分别降低到约42%和20%。较少

In this study, hardware algorithms for highly parallel arithmetic circuits, logic-in-memory VLSI architecture, and low-power, high-speed multiple-valued integrated circuits are considered in detail. The usefulness of the multiple-valued integrated circuits based on level multiplexing is established, and we can develop fundamental technology of a multiple-valued chip family. The major results of this research are shown below:1. Design of highly-parallel multiple-valued arithmetic and logic circuitsThe following three method are proposed to find code assignment for ultimately parallel multiple-valued operation circuits. When a functional specification of a k-ary operation is given by mapping relationship between input and output symbols. (1) Reed-Muller expansion by a sparse matrix, (2) Partion theory, and (3) Hierarchical code assignment using hot codes etc.2. Development of current-mode multiple-valued integrated circuitsThe use of a differential logic circuit with a pair of dual-rail … More inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage. The optimal circuit design is further considered to improve the performance with lower power dissipation. It is made clear that the use of two supply voltages is very useful for the improvement. Moreover, we developed asynchronous and self-checking design methods for the multiple-valued VLSI. As a result, we can obtain fundamental technology for the next-generation multiple-valued VLSI system.3. Development of logic-in-memory multiple-valued VLSI systemA new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass logic is proposed to solve communication bottleneck between memory and logic modules. A multiple-valued sorted data is represented by a threshold voltage of the floating-gate-MOS transistor, so that a single floating-gate MOS transistor is effectively employed for merging a threshold-literal and a pass-switch function. As a typical example of the logic-in-memory VLSI, a fully parallel magnitude compartor is developed. The performance of the proposed VLSI is about 26 times higher than that of a corresponding binary implementation. Moreover, its effective chip area and power dissipation are reduced to about 42% and 20%, respectively. Less