Development of a Chip Family for Ultra-Highly-Parallel Multiple-Valued Integrated Circuits and Its Applications

超高并行多值集成电路芯片族的研制及其应用

基本信息

批准号：
09558025
负责人：
KAMEYAMA Michitaka
金额：
$ 5.38万
依托单位：
TOHOKU UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
1997
资助国家：
日本
起止时间：
1997 至 1999
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-09558025/
关键词：
Dual-Rail Current-Mode Multiple-Valued Integrated Circuit Logic-In-Memory VLSI Self Checking Circuit Highly-Parallel Arithmetic and Logic Circuit Asynchronous Multiple-Valued VLSI Reed-Muller Expansion Partition Theory 分割理論非同期式多値演算回路電流

项目摘要

In this study, hardware algorithms for highly parallel arithmetic circuits, logic-in-memory VLSI architecture, and low-power, high-speed multiple-valued integrated circuits are considered in detail. The usefulness of the multiple-valued integrated circuits based on level multiplexing is established, and we can develop fundamental technology of a multiple-valued chip family. The major results of this research are shown below:1. Design of highly-parallel multiple-valued arithmetic and logic circuitsThe following three method are proposed to find code assignment for ultimately parallel multiple-valued operation circuits. When a functional specification of a k-ary operation is given by mapping relationship between input and output symbols. (1) Reed-Muller expansion by a sparse matrix, (2) Partion theory, and (3) Hierarchical code assignment using hot codes etc.2. Development of current-mode multiple-valued integrated circuitsThe use of a differential logic circuit with a pair of dual-rail … More inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage. The optimal circuit design is further considered to improve the performance with lower power dissipation. It is made clear that the use of two supply voltages is very useful for the improvement. Moreover, we developed asynchronous and self-checking design methods for the multiple-valued VLSI. As a result, we can obtain fundamental technology for the next-generation multiple-valued VLSI system.3. Development of logic-in-memory multiple-valued VLSI systemA new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass logic is proposed to solve communication bottleneck between memory and logic modules. A multiple-valued sorted data is represented by a threshold voltage of the floating-gate-MOS transistor, so that a single floating-gate MOS transistor is effectively employed for merging a threshold-literal and a pass-switch function. As a typical example of the logic-in-memory VLSI, a fully parallel magnitude compartor is developed. The performance of the proposed VLSI is about 26 times higher than that of a corresponding binary implementation. Moreover, its effective chip area and power dissipation are reduced to about 42% and 20%, respectively. Less

在这项研究中，详细考虑了用于高度平行算术电路，内存VLSI架构和低功率高速多价集成电路的硬件算法。建立了基于级别多路复用的多价值集成电路的实用性，我们可以开发多价值芯片家族的基本技术。这项研究的主要结果如下：1。高度并联多价值算术和逻辑电路的设计提出了以下三种方法，以找到最终并行多价值操作电路的代码分配。当k-ary操作的功能规范通过映射输入和输出符号之间的关系给出。（1）通过稀疏矩阵，（2）分区理论和（3）使用热代码等的层次代码分配的芦苇 - 毛刺扩展。2。电流模式多值集成电路的开发使用差分逻辑电路与一对双轨……更多的输入使输入电压摇摆使摇摆小，从而在较低的电源电压下导致高驱动能力。最佳电路设计被进一步考虑以通过较低的功率耗散来提高性能。很明显，使用两个供应电压对于改进非常有用。此外，我们为多价VLSI开发了异步和自我检查设计方法。结果，我们可以为下一代多价VLSI系统获得基本技术3。提出了基于多价值的浮动网状MOS Pass逻辑的内存多值VALSI Systema的逻辑多值VLSI Systema的开发，以解决内存和逻辑模块之间的通信瓶颈。多值分类的数据由浮力山面mos晶体管的阈值电压表示，因此有效地使用了单个浮力栅极MOS晶体管来合并阈值 - 文字和传特切换功能。作为逻辑中的内存VLSI的典型示例，开发了完全平行的幅度比较器。提议的VLSI的性能比相应的二进制实现高约26倍。此外，其有效的芯片面积和功率耗散分别减少到约42％和20％。较少的