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Development of a Chip Family for Ultra-Highly-Parallel Multiple-Valued Integrated Circuits and Its Applications

超高并行多值集成电路芯片族的研制及其应用

基本信息

批准号：
09558025
负责人：
KAMEYAMA Michitaka
金额：
$ 5.38万
依托单位：
TOHOKU UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
1997
资助国家：
日本
起止时间：
1997 至 1999
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-09558025/
关键词：
Dual-Rail Current-Mode Multiple-Valued Integrated Circuit Logic-In-Memory VLSI Self Checking Circuit Highly-Parallel Arithmetic and Logic Circuit Asynchronous Multiple-Valued VLSI Reed-Muller Expansion Partition Theory 分割理論非同期式多値演算回路電流

项目摘要

In this study, hardware algorithms for highly parallel arithmetic circuits, logic-in-memory VLSI architecture, and low-power, high-speed multiple-valued integrated circuits are considered in detail. The usefulness of the multiple-valued integrated circuits based on level multiplexing is established, and we can develop fundamental technology of a multiple-valued chip family. The major results of this research are shown below:1. Design of highly-parallel multiple-valued arithmetic and logic circuitsThe following three method are proposed to find code assignment for ultimately parallel multiple-valued operation circuits. When a functional specification of a k-ary operation is given by mapping relationship between input and output symbols. (1) Reed-Muller expansion by a sparse matrix, (2) Partion theory, and (3) Hierarchical code assignment using hot codes etc.2. Development of current-mode multiple-valued integrated circuitsThe use of a differential logic circuit with a pair of dual-rail … More inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage. The optimal circuit design is further considered to improve the performance with lower power dissipation. It is made clear that the use of two supply voltages is very useful for the improvement. Moreover, we developed asynchronous and self-checking design methods for the multiple-valued VLSI. As a result, we can obtain fundamental technology for the next-generation multiple-valued VLSI system.3. Development of logic-in-memory multiple-valued VLSI systemA new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass logic is proposed to solve communication bottleneck between memory and logic modules. A multiple-valued sorted data is represented by a threshold voltage of the floating-gate-MOS transistor, so that a single floating-gate MOS transistor is effectively employed for merging a threshold-literal and a pass-switch function. As a typical example of the logic-in-memory VLSI, a fully parallel magnitude compartor is developed. The performance of the proposed VLSI is about 26 times higher than that of a corresponding binary implementation. Moreover, its effective chip area and power dissipation are reduced to about 42% and 20%, respectively. Less

在这项研究中，硬件算法的高度并行运算电路，逻辑在内存中的超大规模集成电路架构，低功耗，高速多值集成电路被详细考虑。建立了基于电平复用的多值集成电路的实用性，为多值芯片家族的基础技术的发展奠定了基础。本研究的主要结果如下：1.高度并行多值算术和逻辑电路的设计提出了以下三种方法来找到最终并行多值运算电路的代码分配。当一个k元运算的功能说明由输入输出符号之间的映射关系给出时。(1)通过稀疏矩阵的Reed-Muller展开，（2）分割理论，和（3）使用热码的分层码分配等。电流型多值集成电路的发展--一种双导轨差分逻辑电路的应用 ...更多信息输入使得输入电压摆幅小，这导致在较低电源电压下的高驱动能力。进一步考虑优化电路设计，以提高性能，降低功耗。显然，使用两个电源电压对于改进是非常有用的。此外，我们还发展了多值VLSI的异步和自检设计方法。从而为下一代多值VLSI系统提供了基础技术.基于多值浮栅-MOS通路逻辑的逻辑存储器中VLSI系统的研制为了解决存储器与逻辑模块之间的通信瓶颈，提出了一种新的逻辑存储器中VLSI结构。多值排序数据由浮栅MOS晶体管的阈值电压表示，从而有效地使用单个浮栅MOS晶体管来合并阈值文字和传输开关功能。作为存储器逻辑VLSI的一个典型例子，研制了一个全并行的幅度比较器。所提出的VLSI的性能比相应的二进制实现高约26倍。此外，它的有效芯片面积和功耗分别减少到约42%和20%。少