Development of VLSI Processor Chip Family for Highly-Safe Intelligent Vehicles Based on Optimal Design Mythologies

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Intelligent vehicle applications are expected to be one of promising future system LSI applications. If these applications become realistic, any real-worldapplications will be posslit1e. As typical case studies, intelligent vehicle applications are useful to develop a high-level synthesis methology of system LSI. From the point of view, the following technologies are studied1. VLSI chip family for intelligent vehiclesThe highest performance VLSI chip family is developed for highly-safe intelligent vehicles. These are VLSI processors for stereo vision, optical-flow extraction, path planning and trajectory perdition based on probabilistic inference. These VLSI-oriented algorithms are also discussed to reduce the computational complexity. Moreover, a high-performance field-programmable VLSI which is very superior to the conventional FPGAS is developed2. System integration and intelligent algorithmsSensing of environment information and prediction of the dynamic change are very important t … More echnologies to realize real-world applications. A system integration methology is developed considering measurement and prediction errors. The condition of a sampling period is discussed based on a real-world signal processing model.3. Design theory of VLSI processorsOne of the most serious problems in recent VLSI systems is large delay due to interconnection complexity between memories and processing elements. To solve the problem, a parallel processing module composed of a processing element and a local memory is defined as a basic building block to make interconnection delay as small as possible. Still, there exists propagation delay for data transfer between the modules. A high-level synthesis method considering the data transfer time is discussed on the hardware model, when a data-dependency graph corresponding to a processing algorithm is given. We must simultaneously consider both scheduling and allocation for the time optimization problem under a constraint of achip area. A branch and bound method and a genetic algorithm are effectively employed to find an optimum solution. Extension of the above methologies is also considered to solve the following general problems・Minimization of processing under chip area constraint・Minimization of chip area under processing time constraint・Minimization of dissipation energy under processing time and chip area constraint Less