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Ultra-Highly-Parallel Arithmetic and Logic Circuits and Their Multiple-Valued Integration

超高并行算术逻辑电路及其多值集成

基本信息

批准号：
06452386
负责人：
KAMEYAMA Michitaka
金额：
$ 3.71万
依托单位：
Tohoku University, Graduate School of Information Sciences
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
1994
资助国家：
日本
起止时间：
1994 至 1996
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-06452386/
关键词：
Highly Parallel Arithmetic and Logic Circuit Linear Digital Circuit Reed-Muller Expansion Critical-Path Minimization Redundant Coding Multiple-Valued Current-Mode Integrated Circuit Low Power Multiple-Valued Integrated Circuit 超高並列演算システム多

项目摘要

Highly parallel hardware algorithms based on new data representation and circuit technology are key issues to develop VLSI processors in deep submicron geometry. Local computability and parallelism are one of the most important factors to reduce the critical delay path which determines processor performance.In this research project, multiple-valued redundant encoding method for parallel hardware algorithms were investigated together with the multiple-valued circuit technology. Our concept is that linearlity is fully utilized to make systematic design feasible. Linear combinational circuits are constructed by adders and coefficient multipliers over GF (p).Let us assume that the specifications are given by symbol-level operations. A linear circuit for a unary operation can be always transformed to a highly parallel circuit whose output depends on only 2 input-digits by the matrix transformation called the similar transformation. If all representation matrices are equal each other in k-ar … More y operations, we can obtain consistent sparce matrices for K representation matrices. A symmetrical operation is such a class of operations. However, we cannot always linearize every k-ary specification. To solve the problem, we introduce multiplicated recundant symbols by assigning multiple-valued code vertices to one symbol. A sufficient condition for the symbol-level linearlity is derived to make the redundant multiple-valued code assignment.Extension of the above design method is also discussed in a class of non-linear combinational circuits based on Reed-Muller expansion. If we can obtain a matrix representation of a combinational circuit with a formulation of the product of a constant matrix and variable vectors, design of a highly parallel circuit can be attributed to find a sparce constant matrix. Such class of the combinational circuits is more general, so it will be very useful for the design of practical k-ary operations such as an adder and a multiplier.Another aspect of this research is low-power high performance multiple-valued integrated circuits. A new current-mode multiple-valued MOS integrated circuit is proposed with higher driving capability in comparison with the conventional binary and multiple-valued digital circuits. Moreover, an effective current-source control technique is found which leads to low-power high-speed multiple-valued threshold logic operations. This new circuit technology will be effectively employed for the highly parallel arithmetic and logic circuits developed in this project. Less

基于新数据表示和电路技术的高度并行硬件算法是开发深亚微米几何结构的VLSI处理器的关键问题。局部可计算性和并行性是减少决定处理器性能的关键延迟路径的最重要因素之一。在本研究项目中，结合多值电路技术，研究了并行硬件算法的多值冗余编码方法。我们的理念是充分利用线性使系统设计变得可行。线性组合电路由加法器和系数乘法器在 GF (p) 上构建。让我们假设规范是由符号级运算给出的。用于一元运算的线性电路始终可以通过称为相似变换的矩阵变换变换为高度并行电路，其输出仅取决于 2 个输入数字。如果所有表示矩阵在 k-ar … 更多 y 运算中彼此相等，我们可以获得 K 个表示矩阵的一致稀疏矩阵。对称运算就是这样一类运算。然而，我们不能总是线性化每个 k 元规范。为了解决这个问题，我们通过将多值代码顶点分配给一个符号来引入乘法冗余符号。推导了符号级线性度进行冗余多值码分配的充分条件。本文还讨论了上述设计方法在一类基于Reed-Muller展开的非线性组合电路中的扩展。如果我们能够通过常数矩阵和变量向量的乘积公式获得组合电路的矩阵表示，那么高度并行电路的设计就可以归因于找到稀疏常数矩阵。这类组合电路更为通用，因此对于加法器、乘法器等实际k进制运算的设计非常有用。本研究的另一个方面是低功耗高性能多值集成电路。提出了一种新型电流型多值MOS集成电路，与传统的二进制和多值数字电路相比，具有更高的驱动能力。此外，还发现了一种有效的电流源控制技术，可实现低功耗高速多值阈值逻辑运算。这项新的电路技术将有效地应用于本项目开发的高度并行算术和逻辑电路。较少的