Ultra-Highly-Parallel Arithmetic and Logic Circuits and Their Multiple-Valued Integration

超高并行算术逻辑电路及其多值集成

基本信息

批准号：
06452386
负责人：
KAMEYAMA Michitaka
金额：
$ 3.71万
依托单位：
Tohoku University, Graduate School of Information Sciences
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
1994
资助国家：
日本
起止时间：
1994 至 1996
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-06452386/
关键词：
Highly Parallel Arithmetic and Logic Circuit Linear Digital Circuit Reed-Muller Expansion Critical-Path Minimization Redundant Coding Multiple-Valued Current-Mode Integrated Circuit Low Power Multiple-Valued Integrated Circuit 超高並列演算システム多

项目摘要

Highly parallel hardware algorithms based on new data representation and circuit technology are key issues to develop VLSI processors in deep submicron geometry. Local computability and parallelism are one of the most important factors to reduce the critical delay path which determines processor performance.In this research project, multiple-valued redundant encoding method for parallel hardware algorithms were investigated together with the multiple-valued circuit technology. Our concept is that linearlity is fully utilized to make systematic design feasible. Linear combinational circuits are constructed by adders and coefficient multipliers over GF (p).Let us assume that the specifications are given by symbol-level operations. A linear circuit for a unary operation can be always transformed to a highly parallel circuit whose output depends on only 2 input-digits by the matrix transformation called the similar transformation. If all representation matrices are equal each other in k-ar … More y operations, we can obtain consistent sparce matrices for K representation matrices. A symmetrical operation is such a class of operations. However, we cannot always linearize every k-ary specification. To solve the problem, we introduce multiplicated recundant symbols by assigning multiple-valued code vertices to one symbol. A sufficient condition for the symbol-level linearlity is derived to make the redundant multiple-valued code assignment.Extension of the above design method is also discussed in a class of non-linear combinational circuits based on Reed-Muller expansion. If we can obtain a matrix representation of a combinational circuit with a formulation of the product of a constant matrix and variable vectors, design of a highly parallel circuit can be attributed to find a sparce constant matrix. Such class of the combinational circuits is more general, so it will be very useful for the design of practical k-ary operations such as an adder and a multiplier.Another aspect of this research is low-power high performance multiple-valued integrated circuits. A new current-mode multiple-valued MOS integrated circuit is proposed with higher driving capability in comparison with the conventional binary and multiple-valued digital circuits. Moreover, an effective current-source control technique is found which leads to low-power high-speed multiple-valued threshold logic operations. This new circuit technology will be effectively employed for the highly parallel arithmetic and logic circuits developed in this project. Less

基于新数据表示和电路技术的高度平行的硬件算法是开发深subsicron几何形状中VLSI处理器的关键问题。本地计算和并行性是减少决定处理器性能的关键延迟路径的最重要因素之一。在这项研究项目中，研究了对并行硬件算法的多价值冗余编码方法与多价值电路技术一起研究了。我们的概念是，线性充分利用可使系统设计可行。线性组合电路由GF（P）上的加法器和有能力的乘数构建。LET我们假设规格是由符号级操作给出的。一个单一操作的线性电路可以始终转换为高度平行的电路，该电路仅取决于2个输入数字，即矩阵变换称为相似的转换。如果所有表示矩阵在k-ar中彼此平等……更多的操作，我们可以为K代表物品获得一致的宽松物品。对称操作就是这样的操作。但是，我们不能总是将每个K-ARY规范线性化。为了解决问题，我们通过将多价值代码顶点分配给一个符号来引入多价值的回外符号。得出符号级线性的足够条件是导致冗余多价值代码分配。上述设计方法的扩展还可以在基于Reed-Muller扩展的一类非线性组合电路中讨论。如果我们可以获得具有恒定矩阵和可变矢量乘积的组合电路的矩阵表示，则可以将高度平行电路的设计归因于找到备用的恒定矩阵。这样的组合电路类别更为笼统，因此对于实用的K-ARY操作（例如加法器和乘数）的设计将非常有用。这项研究的另一个方面是低功能高性能多价值集成电路。与传统的二进制和多价值数字电路相比，提出了一个新的电流模式多值MOS集成电路，具有更高的驱动能力。此外，发现有效的电流源控制技术，该技术导致低功率高速多价阈值逻辑操作。这种新的电路技术将有效地用于该项目中开发的高度平行算术和逻辑电路。较少的