Multiple-Valued Reconfigurable VLSI Based on Adaptively Autonomous Operation
基于自适应自主操作的多值可重构VLSI
基本信息
- 批准号:23656230
- 负责人:
- 金额:$ 2.41万
- 依托单位:
- 依托单位国家:日本
- 项目类别:Grant-in-Aid for Challenging Exploratory Research
- 财政年份:2011
- 资助国家:日本
- 起止时间:2011 至 2012
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
A fine-grain multiple-valued reconfigurable VLSI architecture using multiple-valued differential-pair circuits is developed to achieve very high-performance and low- power operations. Multiple-valued signaling is utilized to implement a compact switch block, where multiple-valued signals such as “0", “1", "2" and “3" are transmitted in one line. Also, an autonomous power gating scheme is introduced using two techniques. One is a current-source control based on valid data signal detection. The other is a current-source control such that current sources are turned off within a clock cycle after a logic operation completion signal is detected. Moreover, a register-transfer-level packet routing scheme is introduced to reduce a configuration memory size of a dynamically reconfigurable processor. The register-transfer-driven concept makes the configuration memory size very small, because packets are not required to be provided at all the clock cycles.
提出了一种基于多值差分对电路的细粒度多值可重构VLSI结构,以实现极高性能和低功耗操作。利用多值信令来实现紧凑的开关块,其中诸如“0”、“1”、“2”和“3”的多值信号在一条线路中传输。此外,一个自主的功率门控方案介绍了使用两种技术。一种是基于有效数据信号检测的电流源控制。另一种是电流源控制,使得在检测到逻辑运算完成信号之后在时钟周期内关断电流源。此外,引入寄存器传输级分组路由方案以减小动态可重配置处理器的配置存储器大小。寄存器传输驱动的概念使得配置存储器的大小非常小,因为不需要在所有时钟周期提供分组。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
Current-Source-Sharing Differential-Pair Circuits for a Low-Power Fine-Grain Reconfigurable VLSI Architecture
适用于低功耗细粒度可重构 VLSI 架构的电流源共享差分对电路
- DOI:10.1109/ismvl.2012.13
- 发表时间:2012
- 期刊:
- 影响因子:0
- 作者:Yuusuke Yamaguchi;Yoshinori Tatematsu;Teruo Saito;Ryosuke Ikeda;Jagadish C Mudiganti;Isamu Ogawa and Toshitaka Idehara;Xu Bai and Michitaka Kameyama
- 通讯作者:Xu Bai and Michitaka Kameyama
入力到来とクロックサイクル内論理演算完了の検出に基づく低電力多値リコンフィギャラブルVLSIの自律電流源制御
基于时钟周期内输入到达和逻辑操作完成检测的低功耗多级可重构VLSI自主电流源控制
- DOI:
- 发表时间:2011
- 期刊:
- 影响因子:0
- 作者:Teruo SAITO;Shinya OGASAWARA;Naoki YAMADA;Shinji IKEUCHI;Yoshinori TATEMATSU;Ryosuke IKEDA;Isamu OGAWA and Vladimir N. MANUILOV;藤岡周与,亀山充隆;Yuusuke Yamaguchi;白旭,亀山充隆;木皿祥吾,亀山充隆;Teruo Saito;藤岡与周,瀧沢翔,亀山充隆;Teruo Saito;木皿祥吾,亀山充隆
- 通讯作者:木皿祥吾,亀山充隆
多値スイッチブロックと2値論理演算モジュールから構成されるビットシリアルリコンフィギャラブルVLSI
由多值开关块和二进制逻辑运算模块组成的位串行可重构VLSI
- DOI:
- 发表时间:2011
- 期刊:
- 影响因子:0
- 作者:Teruo SAITO;Shinya OGASAWARA;Naoki YAMADA;Shinji IKEUCHI;Yoshinori TATEMATSU;Ryosuke IKEDA;Isamu OGAWA and Vladimir N. MANUILOV;藤岡周与,亀山充隆;Yuusuke Yamaguchi;白旭,亀山充隆;木皿祥吾,亀山充隆;Teruo Saito;藤岡与周,瀧沢翔,亀山充隆;Teruo Saito;木皿祥吾,亀山充隆;白旭,亀山充隆
- 通讯作者:白旭,亀山充隆
コンフィグレーションメモリサイズの減少を指向したパケット転送に基づく動的再構成VLSIプロセッサの構成
基于数据包转发的动态可重新配置 VLSI 处理器配置,旨在减少配置内存大小
- DOI:
- 发表时间:2012
- 期刊:
- 影响因子:0
- 作者:Teruo SAITO;Shinya OGASAWARA;Naoki YAMADA;Shinji IKEUCHI;Yoshinori TATEMATSU;Ryosuke IKEDA;Isamu OGAWA and Vladimir N. MANUILOV;藤岡周与,亀山充隆
- 通讯作者:藤岡周与,亀山充隆
Prospects of Post-Binary ULSI Systems and Novel Reconfigurable VLSI Architectures
后二进制 ULSI 系统和新型可重构 VLSI 架构的前景
- DOI:
- 发表时间:2011
- 期刊:
- 影响因子:0
- 作者:Yuusuke YAMAGUCHI;Yoshinori TATEMATSU;Teruo SAITO;Ryosuke IKEDA;Jagadish C. MUDIGANTI;Isamu OGAWA and Toshitaka IDEHARA;Michitaka Kameyama;Michitaka Kameyama
- 通讯作者:Michitaka Kameyama
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KAMEYAMA Michitaka其他文献
KAMEYAMA Michitaka的其他文献
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{{ truncateString('KAMEYAMA Michitaka', 18)}}的其他基金
Optimal VLSI Design for a Highly-Safe Intelligent Vehicle Based on a System Integration Theory
基于系统集成理论的高安全智能汽车超大规模集成电路优化设计
- 批准号:
17300009 - 财政年份:2005
- 资助金额:
$ 2.41万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
Development of VLSI Processor Chip Family for Highly-Safe Intelligent Vehicles Based on Optimal Design Mythologies
基于优化设计神话的高安全智能汽车VLSI处理器芯片系列开发
- 批准号:
12555119 - 财政年份:2000
- 资助金额:
$ 2.41万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
Development of a Chip Family for Ultra-Highly-Parallel Multiple-Valued Integrated Circuits and Its Applications
超高并行多值集成电路芯片族的研制及其应用
- 批准号:
09558025 - 财政年份:1997
- 资助金额:
$ 2.41万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
High-Level Synthesis of High-Performance VLSI Processors for Intelligent Integrated System
智能集成系统高性能VLSI处理器的高水平综合
- 批准号:
09450162 - 财政年份:1997
- 资助金额:
$ 2.41万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
Study on Multiple-Valued VLSI Processors for a Highly Safe Intelligent Vehicle
高安全智能汽车多值VLSI处理器研究
- 批准号:
07558151 - 财政年份:1995
- 资助金额:
$ 2.41万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
Ultra-Parallel and Ultra-High-Speed Architecture for Ultimate Integration
超并行、超高速架构,实现终极集成
- 批准号:
07248102 - 财政年份:1995
- 资助金额:
$ 2.41万 - 项目类别:
Grant-in-Aid for Scientific Research on Priority Areas
Ultra-Highly-Parallel Arithmetic and Logic Circuits and Their Multiple-Valued Integration
超高并行算术逻辑电路及其多值集成
- 批准号:
06452386 - 财政年份:1994
- 资助金额:
$ 2.41万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
Development of VLSI Processors for Robot Control with Ultra-High Performance in the Arithmetic Delay
超高性能算术延迟机器人控制VLSI处理器的开发
- 批准号:
04555076 - 财政年份:1992
- 资助金额:
$ 2.41万 - 项目类别:
Grant-in-Aid for Developmental Scientific Research (B)
Study on Post-Binary ULSI Sstems
后二元ULSI系统研究
- 批准号:
04044024 - 财政年份:1992
- 资助金额:
$ 2.41万 - 项目类别:
Grant-in-Aid for international Scientific Research
Ultra-Many-Valued, Highly Parallel Computing System for Biochip Implementation
用于生物芯片实现的超多值、高度并行计算系统
- 批准号:
03805033 - 财政年份:1991
- 资助金额:
$ 2.41万 - 项目类别:
Grant-in-Aid for General Scientific Research (C)