Study on Multiple-Valued VLSI Processors for a Highly Safe Intelligent Vehicle

对于下一代超级芯片，不仅计算机世界的应用，而且现实世界的应用将是重要的目标。在实际应用中，数据流通过真实的世界，通过控制动作将现实环境改变为期望的状态。典型应用是机器人技术、智能车辆、工厂自动化、实时仪表和控制系统等。本研究课题主要研究基于新型多值集成电路的高性能超大规模集成电路处理器及其关键技术。（1）用于高速碰撞检测和三维仪器的VLSI处理器在车辆和障碍物之间的碰撞检测操作中，不仅在坐标变换中而且在车辆和障碍物像素之间的匹配操作中本质上需要高计算能力。在所提出的高速碰撞检测的VLSI处理器中， ...更多信息 引入了可存储器来存储车辆像素信息，使得匹配操作大大加速。由于车辆像素信息是预先确定的，并且不会改变，因此提出了基于ROM单元的高性能CAM。基于二维矢量旋转和矩阵乘法，提出了一种高速坐标变换的并行流水线结构，并提出了一种适用于高速三维仪器的高性能VLSI结构。由于候选块中的像素重叠，因此这些像素值由处理元件（PE）的2-D阵列重复使用。通过使用2-D PE阵列，仅需要本地通信，因为图像块是像素值的2-D阵列。此外，还提出了一种新的存储器交错技术，以并发访问帧存储器。（2）低功耗电流模式多值集成电路提出了一种新的电流源控制技术，用于设计低电源电压下的低功耗高速多值电流模式（MVCM）集成电路。使用具有一对双轨互补输入的差分逻辑电路（DLC）使得输入信号电压摆幅小，这导致在较低电源电压下的高驱动能力，同时具有大的静态功率损耗。在建议的DLC使用开关电流控制，静态功耗大大降低，因为在非有源电路块中的电流源被切断。在电流控制中，不需要额外的晶体管来控制电流源，因为在阈值检测器中已经使用了电流控制电路。作为算术电路的一个典型例子，本文还设计了一个基于0.8 μ mCMOS工艺的1.5V电源电压的54*54位乘法器。在<1.3>归一化功耗下，其性能比二进制最快乘法器快约1/4。（3）高性能多值内容可寻址存储器及其应用提出了一种新的高密度多值内容可寻址存储器（CAM），用于高并行搜索操作。多值存储数据对应于浮栅MOS晶体管的阈值电压，从而可以仅使用单个晶体管来设计单元电路。由于在一字电路中使用一条匹配线来执行多输入线与操作，因此可以同时获得多位数据之间的幅度比较结果。结果，尽管是单晶体管单元电路和单匹配线结构，但可以通过仅（n+1）个步骤来执行具有n位的一个世界幅度比较，这使得CAM单元阵列的外围电路很小。典型应用表明，该非易失性CAM可作为高速碰撞检测和高度并行的碰撞检测规则匹配等实际应用的硬件加速器，此外，本文还提出了一种新的用于高速细胞逻辑图像处理的专用四值CAM。CAM单元中的通用文字用于同时将4值输入值与各种模板模式进行比较。具有4值数据存储能力的通用文字单元电路可以仅由几个浮栅MOS晶体管实现，因为单元功能由简单的阈值操作以及逻辑值转换来执行。其结果是，在建议的CAM阵列的有效单元面积大大减少相比，在相应的二进制CAM为基础的实施。少

For next-generation super chips, not only computer-worldapplications but also real-world applications will be important targets. In the real-world applicatins, thers is data flow passing through the real world, so that the real-world environment is changed to be the desired states by control actions. The typical applications are robotics, intelligent vehicle, factory automation, real-time instrumentation and control systems, and so on. In this reaearch project high-performance VLSI processors and their key technologies based on new multiple-valued integrated circuits have been developed an follows :(1)VLSI processors for high-speed collision detection and 3-Dimensional instrumentationIn the collision-detection operation between a vehicle and obstacles, high-computational power is essentially required in not only coordinate transformation but also matching operation between vehicle and obstacle pixels. In the proposed VLSI processor for high-speed collision detection, a content-addressa … More ble memory is introduced to store vehicle pixel information, so that the matching operation is drastically accelerated. Since vehicle pixel information is predetermined and not changed, the high-performance CAM based on a ROM cell is proposed. A parallel and pipelined architecture for the high-speed coordinate transformation is also proposed based on two-dimensional vector rotations and matrix multiplications.On the other hand, a high-performance VLSI architecture with an efficient memory access scheme is proposed for high-speed 3-D instrumentation. Since pixels in candidate blocks overlap, these pixel values are used repetitively by a 2-D array of processing elements (PEs). By using the 2-D PE array, only local communications are required since the image block is a 2-D array of pixel values. Moreover, a new memory-interleave technique is also proposed to concurrently access the frame memory.(2)Low-Power Current-Mode Multiple-Valued Integrated CircuitsA new current-source control technique is proposed to design a low-power high-speed multiple-valued current-mode (MVCM) integrated circuit in a low supply voltage. The use of a defferential logic circuit (DLC) with a pair of dual-rail complementary inputs makes an input signal-voltage swing small, which results in a high driving capability at a lower supply voltage while having large static power dessipation. In the proposed DLC using switched current control, the static power dissipation is greatly reduced because current sources in non-active circuit blocks are switched off. In the current control, no additional transistors are required to control the current sources because a current-control circuit is already used in the threshold detector. As a typical example of arithmetic circuits, a new 1.5V-supply 54*54-bit multiplier based on a standard 0.8-um CMOS technology is also designed. Its performance is about ^<1.3> times faster than of a binary fastest multiplier under the normalized powerdissipation.(3)High-Performance Multiple-Valued Content-Addressable Memory and Its ApplicationA new high-density multiple-valued content-addressable memory (CAM) is proposed for highly parallel search operations. Multiple-valued stored data correspond to the threshold voltage of a floating-gate MOS transistor, so that the cell circuit can be designed using only a single transistor. Since a single match line in a one-word circuit is used for performing a multi-input wired AND opearion, the magnitude comparison result between multi-digit data can be obtained simultaneously. As a result, a one-world magnitude comparison with n digits can be performed by just (n+1) steps in spite of a single-transistor cell circuit and single-match-line architecture, which makes the peripheral circuit of a CAM cell array small. Moreover, typical applications clearly demonstrate that theproposed non-volatile CAM is useful as a hardware accelerator for various real-world applications such as high-speed collision detection and highly parallel danger-detection rule matching.Moreover, a new special-purpose 4-valued CAM is also proposed for high-speed cellular logic image processing. A universal literal in CAM cell is used to compare a 4-valued input value with various template patterns simultaneously. The universal-literal cell circuit with 4-valued data storage capability can be implemented by just a few floating-gate MOS transistors, since the cell function is performed by simple threshold operations together with logic-value conversion. As a result, the effective cell area in the proposed CAM array is greatly reduced in comparison with that in a corresponding binary CAM-based implementation. Less