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Development of VLSI Processors for Robot Control with Ultra-High Performance in the Arithmetic Delay

超高性能算术延迟机器人控制VLSI处理器的开发

基本信息

批准号：
04555076
负责人：
KAMEYAMA Michitaka
金额：
$ 5.82万
依托单位：
Tohoku University, Graduate School of Information Sciences
依托单位国家：
日本
项目类别：
Grant-in-Aid for Developmental Scientific Research (B)
财政年份：
1992
资助国家：
日本
起止时间：
1992 至 1994
项目状态：
已结题

项目摘要

For next-generation super chips, not only computer-world applications but also real-world applications will be important targets. In the real-world applications, there is data flow passing through the real world, so that the real-world environment is changed to be the desired states by control actions. The typical applications are robotics. Especially, the target architectures rely incresingly on VLSI processors having a high degree of spatial parallelism. Such processors, capable of providing both high throughput and low latency, will be essential components in robot control because they have to respond quickly to the real-world events. In this research project, the following highest performance VLSI processorshave been developed for the first time in the world.(1) Minimum-Latency Linear Array VLSI ProcessorsThe key concept to minimize the latency is that each each processor element generates its output data emmediately after its input data become available, with 100% utilization of i … More ts arithmetic unit. The developed porcessors based on the concept are the inverse dynamics processor and the FFT processor for robot vision. These performances are much higher than those of the conventional ones.(2) Reconfigurable Parallel VLSI ProcessorIn each processor element, a switch circuit is used to change the connection between the multipliers and adders, so that the multiple-input add-multiply can be performed effectively without communication overhead in the data transfer. For an example, the differential kinematics computation can be performed about 100 times faster in comparison with the convential parallel DSP aruchiteture.(3) Bus-connected parallel VLSI processorsTo reduce the latency, the number of communication steps is minimized by its optimal allocation formulated in an integer programming. Moreover, not only parallel operations in memory access and execuition of a task but also parallel data transfer is realized to make the communication cycle time small. To verify its validity, the universal processor is evaluated on the computation of dynamic control. Less

对于下一代超级芯片，不仅计算机世界的应用，而且现实世界的应用将是重要的目标。在实际应用中，存在着数据流通过真实的世界，从而通过控制动作将现实环境改变为期望的状态。典型的应用是机器人。特别是，目标体系结构越来越依赖于具有高度空间并行性的VLSI处理器。这种处理器能够提供高吞吐量和低延迟，将成为机器人控制中的重要组件，因为它们必须快速响应现实世界的事件。在本研究项目中，在世界上首次开发了以下最高性能的VLSI处理器。(1)最小延迟线性阵列VLSI处理器最小延迟的关键概念是每个处理器元件在其输入数据可用后立即生成其输出数据，i的利用率为100%。 ...更多信息 ts算术单元。在此基础上开发了机器人视觉逆动力学处理器和FFT处理器。这些性能远远高于传统的。(2)可重构并行VLSI处理器在每个处理器单元中，使用开关电路来改变乘法器和加法器之间的连接，从而可以有效地执行多输入加-乘，而在数据传输中没有通信开销。例如，与传统的并行DSP架构相比，微分运动学计算的执行速度可以快约100倍。(3)总线连接的并行VLSI处理器为了减少延迟，通信步骤的数量被最小化，其最优分配用整数规划公式表示。此外，不仅在存储器访问和任务执行中实现了并行操作，而且还实现了并行数据传输，使得通信周期时间小。为了验证其有效性，通用处理器进行了评估的动态控制计算。少