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Study on Post-Binary ULSI Sstems

后二元ULSI系统研究

基本信息

批准号：
04044024
负责人：
KAMEYAMA Michitaka
金额：
$ 2.18万
依托单位：
Tohoku University, Graduate School of Information Sciences
依托单位国家：
日本
项目类别：
Grant-in-Aid for international Scientific Research
财政年份：
1992
资助国家：
日本
起止时间：
1992 至 1993
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-04044024/
关键词：
Intelligent Integrated Systems Highly Parallel Multiple-Valued Arithmetic and Logic Circuits Linear Digital System Ultra Fine Integrated Circuits Small Critical-Delay Path Small Interconnection Delay Device-Model Based Electronics Multiple-V

项目摘要

The present binary VLSI systems will be confronted with many serious problems in an ultimately fine geometry feature size. Some of them are listed below :(1) Interconnection delay is prominent limit on the performance in the deep submicron integrated circuits.(2) For low-voltage operations, noises caused inside a chip should be reduced.(3) Parallel procesing performance is limited by data communications between processing elements.(4) Large scale design is essential at various levels such as logic design, test, circuit design and physical design.(5) New phenomena such as tunnneling and quantum effects will be caused in microelectronics devices, which is usually assumed to be inconvenient effects for binary digital operations.Multiple-valued digital processing and its integration are expected to be one of the most effective solutions for the above problems. The objective of this research is to demonstrate theories, new developments and techniques in multiple-valued integrated circuits a … More nd their applications. Especially, the delay time due to global communications between functional modules is one of the most important factors to determine the total performance In ULSI Processors for the applications of intelligent integrated systems.Several concrete advantages of multiple-valued digital procssing technology have been established in deep submicron geometry. They are classified to the device and circuit level, the arithmetic and logic algortihm level, and the system application level. In the device and circuit level, we have demonstrated that the new area called device-model based electronics becomes very important to activate the new direction of the device development suitable for multiple-valued operations. In the alogorithm level, we have proposed a new design method for highly parallel operation circuits based on a linear concept. In the system application level, we have designed a new multiple-valued ULSI processor for digital control with spatially parallel structure. Further, we have proposed a universal super chip for intelligent integrated systems with very flexible network structure. Less

目前的二进制VLSI系统在最终精细几何特征尺寸方面将面临许多严重的问题。互连线延迟是深亚微米集成电路性能的主要限制因素。(2)对于低电压操作，应减少芯片内部产生的噪声。(3)并行处理性能受到处理单元之间的数据通信的限制。(4)大规模设计在逻辑设计、测试、电路设计和物理设计等各个层面都是必不可少的。(5)微电子器件中会产生隧道效应和量子效应等新现象，这些现象通常被认为是二进制数字运算的不便之处，多值数字处理及其集成有望成为解决这些问题的最有效的方法之一。本研究的目的是展示多值集成电路的理论、新发展和技术， ...更多信息他们的应用程序。特别是在智能集成系统中，由于功能模块之间的全局通信而引起的延迟时间是决定ULSI处理器总体性能的重要因素之一，多值数字处理技术在深亚微米几何中的具体优势已经得到证实。它们分为器件和电路级、算术和逻辑算法级以及系统应用级。在器件和电路层面，我们已经证明，称为基于器件模型的电子学的新领域对于激活适合于多值运算的器件开发的新方向变得非常重要。在算法级，我们提出了一种基于线性概念的高度并行运算电路的设计方法。在系统应用层面，我们设计了一种新的多值ULSI数字控制处理器，具有空间并行结构。此外，我们提出了一个通用的超级芯片的智能集成系统具有非常灵活的网络结构。少