Study on Post-Binary ULSI Sstems

后二元ULSI系统研究

基本信息

批准号：
04044024
负责人：
KAMEYAMA Michitaka
金额：
$ 2.18万
依托单位：
Tohoku University, Graduate School of Information Sciences
依托单位国家：
日本
项目类别：
Grant-in-Aid for international Scientific Research
财政年份：
1992
资助国家：
日本
起止时间：
1992 至 1993
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-04044024/
关键词：
Intelligent Integrated Systems Highly Parallel Multiple-Valued Arithmetic and Logic Circuits Linear Digital System Ultra Fine Integrated Circuits Small Critical-Delay Path Small Interconnection Delay Device-Model Based Electronics Multiple-V

项目摘要

The present binary VLSI systems will be confronted with many serious problems in an ultimately fine geometry feature size. Some of them are listed below :(1) Interconnection delay is prominent limit on the performance in the deep submicron integrated circuits.(2) For low-voltage operations, noises caused inside a chip should be reduced.(3) Parallel procesing performance is limited by data communications between processing elements.(4) Large scale design is essential at various levels such as logic design, test, circuit design and physical design.(5) New phenomena such as tunnneling and quantum effects will be caused in microelectronics devices, which is usually assumed to be inconvenient effects for binary digital operations.Multiple-valued digital processing and its integration are expected to be one of the most effective solutions for the above problems. The objective of this research is to demonstrate theories, new developments and techniques in multiple-valued integrated circuits a … More nd their applications. Especially, the delay time due to global communications between functional modules is one of the most important factors to determine the total performance In ULSI Processors for the applications of intelligent integrated systems.Several concrete advantages of multiple-valued digital procssing technology have been established in deep submicron geometry. They are classified to the device and circuit level, the arithmetic and logic algortihm level, and the system application level. In the device and circuit level, we have demonstrated that the new area called device-model based electronics becomes very important to activate the new direction of the device development suitable for multiple-valued operations. In the alogorithm level, we have proposed a new design method for highly parallel operation circuits based on a linear concept. In the system application level, we have designed a new multiple-valued ULSI processor for digital control with spatially parallel structure. Further, we have proposed a universal super chip for intelligent integrated systems with very flexible network structure. Less

目前的二进制VLSI系统将面临许多最终精细的几何特征大小的严重问题。其中一些在下面列出：（1）互连延迟是对深subsicron集成电路的性能的显着限制。（2）对于低压操作，应降低芯片内部引起的噪声。（3）平行处理性能受到处理元素之间的数据通信的限制。量子效应将是在微电子设备中引起的，通常认为这是二进制数字操作的不方便效应。多个价值的数字处理及其集成有望成为上述问题最有效的解决方案之一。这项研究的目的是在多价值综合电路中证明理论，新的发展和技术……更多的应用程序。特别是，由于功能模块之间的全球通信导致的延迟时间是确定ULSI处理器在智能集成系统应用中的总绩效的最重要因素之一。在深subsicron几何形状中已经建立了多价值数字procssist技术的多个多价值数字procssing技术的优势。它们分类为设备和电路级别，算术和逻辑AlgortIHM级别以及系统应用程序级别。在设备和电路级别中，我们证明了称为基于设备模型的电子设备的新区域对于激活适合多价值操作的设备开发的新方向非常重要。在Alogorithm级别，我们为基于线性概念提出了一种用于高度平行操作电路的新设计方法。在系统应用程序级别中，我们设计了一个新的多价值ULSI处理器，用于具有空间并行结构的数字控制。此外，我们为具有非常灵活的网络结构的智能集成系统提出了一个通用的超级芯片。较少的